Lines Matching refs:mec
4405 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); in gfx_v10_0_mec_fini()
4406 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); in gfx_v10_0_mec_fini()
4436 &adev->gfx.mec.hpd_eop_obj, in gfx_v10_0_mec_init()
4437 &adev->gfx.mec.hpd_eop_gpu_addr, in gfx_v10_0_mec_init()
4447 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); in gfx_v10_0_mec_init()
4448 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v10_0_mec_init()
4460 &adev->gfx.mec.mec_fw_obj, in gfx_v10_0_mec_init()
4461 &adev->gfx.mec.mec_fw_gpu_addr, in gfx_v10_0_mec_init()
4471 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); in gfx_v10_0_mec_init()
4472 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); in gfx_v10_0_mec_init()
4681 int mec, int pipe, int queue) in gfx_v10_0_compute_ring_init() argument
4690 ring->me = mec + 1; in gfx_v10_0_compute_ring_init()
4697 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr in gfx_v10_0_compute_ring_init()
4703 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) in gfx_v10_0_compute_ring_init()
4728 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v10_0_alloc_ip_dump()
4729 adev->gfx.mec.num_queue_per_pipe; in gfx_v10_0_alloc_ip_dump()
4771 adev->gfx.mec.num_mec = 2; in gfx_v10_0_sw_init()
4772 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v10_0_sw_init()
4773 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v10_0_sw_init()
4786 adev->gfx.mec.num_mec = 2; in gfx_v10_0_sw_init()
4787 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v10_0_sw_init()
4788 adev->gfx.mec.num_queue_per_pipe = 4; in gfx_v10_0_sw_init()
4794 adev->gfx.mec.num_mec = 1; in gfx_v10_0_sw_init()
4795 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v10_0_sw_init()
4796 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v10_0_sw_init()
4939 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v10_0_sw_init()
4940 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v10_0_sw_init()
4941 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v10_0_sw_init()
6693 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & in gfx_v10_0_cp_compute_load_microcode()
6696 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); in gfx_v10_0_cp_compute_load_microcode()
7184 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v10_0_kcq_init_queue()
7185 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v10_0_kcq_init_queue()
7188 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v10_0_kcq_init_queue()
7189 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v10_0_kcq_init_queue()
9254 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v10_0_set_priv_reg_fault_state()
9255 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v10_0_set_priv_reg_fault_state()
9300 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v10_0_set_bad_op_fault_state()
9301 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v10_0_set_bad_op_fault_state()
9671 adev->gfx.mec.num_mec, in gfx_v10_ip_print()
9672 adev->gfx.mec.num_pipe_per_mec, in gfx_v10_ip_print()
9673 adev->gfx.mec.num_queue_per_pipe); in gfx_v10_ip_print()
9675 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v10_ip_print()
9676 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v10_ip_print()
9677 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v10_ip_print()
9741 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v10_ip_dump()
9742 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v10_ip_dump()
9743 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v10_ip_dump()