Lines Matching refs:GC
125 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),
126 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),
127 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3),
128 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1),
129 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2),
130 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3),
131 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1),
132 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1),
133 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT),
134 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT),
135 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT),
136 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2),
137 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2),
138 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS),
139 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR),
140 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0),
141 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE),
142 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
143 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR),
144 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE),
145 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR),
146 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR),
147 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_BASE),
148 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_RPTR),
149 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_WPTR),
150 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
151 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ),
152 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
153 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
154 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),
155 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO),
156 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI),
157 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ),
158 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS),
159 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS),
160 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS),
161 SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT),
162 SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT),
163 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS),
164 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2),
165 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS),
166 SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS),
167 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS),
168 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES),
169 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS),
170 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS),
171 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL),
172 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS),
173 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),
174 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),
175 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL),
176 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR),
177 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR),
178 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR),
179 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR),
180 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR),
181 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS),
183 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
184 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
185 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
186 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
187 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
188 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
189 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
190 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
192 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0),
193 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1),
194 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2),
195 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3),
196 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE4),
197 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE5)
202 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID),
203 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE),
204 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY),
205 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY),
206 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM),
207 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE),
208 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI),
209 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR),
210 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR),
211 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI),
212 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),
213 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL),
214 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR),
215 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI),
216 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR),
217 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL),
218 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST),
219 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR),
220 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI),
221 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL),
222 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR),
223 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR),
224 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS),
225 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO),
226 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI),
227 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL),
228 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET),
229 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE),
230 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET),
231 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE),
232 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE),
233 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR),
234 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM),
235 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO),
236 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI),
237 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
238 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
239 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET),
240 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS),
242 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
243 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
244 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
245 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
246 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
247 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
248 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
249 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
254 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE),
255 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID),
256 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY),
257 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM),
258 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE),
259 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI),
260 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET),
261 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL),
262 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR),
263 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR),
264 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI),
265 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST),
266 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED),
267 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL),
268 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0),
269 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0),
270 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR),
271 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI),
272 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO),
273 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI),
274 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
275 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
276 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
277 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
278 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),
280 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
281 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
282 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
283 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
284 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
285 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
286 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
287 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
288 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
289 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
290 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
291 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
292 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
293 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
294 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
295 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
299 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000)
304 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010),
305 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010),
306 SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
307 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988),
308 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007),
309 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008),
310 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100),
311 SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000),
312 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a)
561 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); in gfx_v11_0_ring_test_ring()
867 …ctx_reg_offset = SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_RE… in gfx_v11_0_get_csb_buffer()
893 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); in gfx_v11_0_init_rlcg_reg_access_ctrl()
894 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); in gfx_v11_0_init_rlcg_reg_access_ctrl()
895 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); in gfx_v11_0_init_rlcg_reg_access_ctrl()
896 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); in gfx_v11_0_init_rlcg_reg_access_ctrl()
897 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); in gfx_v11_0_init_rlcg_reg_access_ctrl()
898 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); in gfx_v11_0_init_rlcg_reg_access_ctrl()
899 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); in gfx_v11_0_init_rlcg_reg_access_ctrl()
975 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, in wave_read_ind()
978 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); in wave_read_ind()
985 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, in wave_read_regs()
991 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); in wave_read_regs()
1513 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); in gfx_v11_0_rlc_backdoor_autoload_enable()
1514 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); in gfx_v11_0_rlc_backdoor_autoload_enable()
1516 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); in gfx_v11_0_rlc_backdoor_autoload_enable()
1955 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); in gfx_v11_0_select_se_sh()
1962 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regCC_GC_SA_UNIT_DISABLE); in gfx_v11_0_get_sa_active_bitmap()
1966 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGC_USER_SA_UNIT_DISABLE); in gfx_v11_0_get_sa_active_bitmap()
1981 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); in gfx_v11_0_get_rb_active_bitmap()
1985 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); in gfx_v11_0_get_rb_active_bitmap()
2050 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); in gfx_v11_0_init_compute_vmid()
2051 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); in gfx_v11_0_init_compute_vmid()
2054 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); in gfx_v11_0_init_compute_vmid()
2056 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); in gfx_v11_0_init_compute_vmid()
2066 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0); in gfx_v11_0_init_compute_vmid()
2067 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0); in gfx_v11_0_init_compute_vmid()
2068 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0); in gfx_v11_0_init_compute_vmid()
2069 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0); in gfx_v11_0_init_compute_vmid()
2084 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0); in gfx_v11_0_init_gds_vmid()
2085 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0); in gfx_v11_0_init_gds_vmid()
2086 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0); in gfx_v11_0_init_gds_vmid()
2087 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0); in gfx_v11_0_init_gds_vmid()
2099 uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) | in gfx_v11_0_get_tcc_info()
2100 RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE); in gfx_v11_0_get_tcc_info()
2113 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); in gfx_v11_0_constants_init()
2121 tmp = RREG32_SOC15(GC, 0, regTA_CNTL2); in gfx_v11_0_constants_init()
2131 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); in gfx_v11_0_constants_init()
2137 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); in gfx_v11_0_constants_init()
2156 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); in gfx_v11_0_get_cpg_int_cntl()
2158 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); in gfx_v11_0_get_cpg_int_cntl()
2177 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); in gfx_v11_0_get_cpc_int_cntl()
2179 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); in gfx_v11_0_get_cpc_int_cntl()
2181 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); in gfx_v11_0_get_cpc_int_cntl()
2183 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); in gfx_v11_0_get_cpc_int_cntl()
2203 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v11_0_enable_gui_idle_interrupt()
2212 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); in gfx_v11_0_enable_gui_idle_interrupt()
2222 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, in gfx_v11_0_init_csb()
2224 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, in gfx_v11_0_init_csb()
2226 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); in gfx_v11_0_init_csb()
2233 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); in gfx_v11_0_rlc_stop()
2236 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); in gfx_v11_0_rlc_stop()
2241 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v11_0_rlc_reset()
2243 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v11_0_rlc_reset()
2252 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); in gfx_v11_0_rlc_smu_handshake_cntl()
2266 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); in gfx_v11_0_rlc_smu_handshake_cntl()
2276 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v11_0_rlc_start()
2285 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); in gfx_v11_0_rlc_enable_srm()
2288 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); in gfx_v11_0_rlc_enable_srm()
2302 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, in gfx_v11_0_load_rlcg_microcode()
2306 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, in gfx_v11_0_load_rlcg_microcode()
2309 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlcg_microcode()
2325 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); in gfx_v11_0_load_rlc_iram_dram_microcode()
2330 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, in gfx_v11_0_load_rlc_iram_dram_microcode()
2334 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlc_iram_dram_microcode()
2340 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); in gfx_v11_0_load_rlc_iram_dram_microcode()
2344 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, in gfx_v11_0_load_rlc_iram_dram_microcode()
2348 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlc_iram_dram_microcode()
2350 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); in gfx_v11_0_load_rlc_iram_dram_microcode()
2353 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); in gfx_v11_0_load_rlc_iram_dram_microcode()
2369 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0); in gfx_v11_0_load_rlcp_rlcv_microcode()
2374 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA, in gfx_v11_0_load_rlcp_rlcv_microcode()
2378 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlcp_rlcv_microcode()
2380 tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); in gfx_v11_0_load_rlcp_rlcv_microcode()
2382 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp); in gfx_v11_0_load_rlcp_rlcv_microcode()
2388 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0); in gfx_v11_0_load_rlcp_rlcv_microcode()
2393 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA, in gfx_v11_0_load_rlcp_rlcv_microcode()
2397 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlcp_rlcv_microcode()
2399 tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL); in gfx_v11_0_load_rlcp_rlcv_microcode()
2401 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp); in gfx_v11_0_load_rlcp_rlcv_microcode()
2452 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); in gfx_v11_0_rlc_resume()
2455 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); in gfx_v11_0_rlc_resume()
2478 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache()
2480 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); in gfx_v11_0_config_me_cache()
2484 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache()
2499 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); in gfx_v11_0_config_me_cache()
2504 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); in gfx_v11_0_config_me_cache()
2507 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, in gfx_v11_0_config_me_cache()
2509 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, in gfx_v11_0_config_me_cache()
2522 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache()
2524 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); in gfx_v11_0_config_pfp_cache()
2528 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache()
2543 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); in gfx_v11_0_config_pfp_cache()
2548 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); in gfx_v11_0_config_pfp_cache()
2551 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, in gfx_v11_0_config_pfp_cache()
2553 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, in gfx_v11_0_config_pfp_cache()
2566 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_config_mec_cache()
2569 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); in gfx_v11_0_config_mec_cache()
2573 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_config_mec_cache()
2588 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); in gfx_v11_0_config_mec_cache()
2592 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v11_0_config_mec_cache()
2595 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, in gfx_v11_0_config_mec_cache()
2597 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, in gfx_v11_0_config_mec_cache()
2613 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, in gfx_v11_0_config_pfp_cache_rs64()
2615 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, in gfx_v11_0_config_pfp_cache_rs64()
2618 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2622 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2630 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2643 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2645 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2648 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2663 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, in gfx_v11_0_config_pfp_cache_rs64()
2666 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, in gfx_v11_0_config_pfp_cache_rs64()
2673 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2680 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2689 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2691 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, in gfx_v11_0_config_pfp_cache_rs64()
2693 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, in gfx_v11_0_config_pfp_cache_rs64()
2699 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2702 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2705 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2707 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2710 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2735 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, in gfx_v11_0_config_me_cache_rs64()
2737 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, in gfx_v11_0_config_me_cache_rs64()
2740 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); in gfx_v11_0_config_me_cache_rs64()
2744 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2752 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2765 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2767 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2771 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2786 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, in gfx_v11_0_config_me_cache_rs64()
2789 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, in gfx_v11_0_config_me_cache_rs64()
2796 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_me_cache_rs64()
2803 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2812 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2814 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, in gfx_v11_0_config_me_cache_rs64()
2816 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, in gfx_v11_0_config_me_cache_rs64()
2822 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v11_0_config_me_cache_rs64()
2825 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2828 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2830 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2833 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2858 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2862 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v11_0_config_mec_cache_rs64()
2864 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2867 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); in gfx_v11_0_config_mec_cache_rs64()
2873 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2); in gfx_v11_0_config_mec_cache_rs64()
2874 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, in gfx_v11_0_config_mec_cache_rs64()
2877 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, in gfx_v11_0_config_mec_cache_rs64()
2880 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, in gfx_v11_0_config_mec_cache_rs64()
2883 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr); in gfx_v11_0_config_mec_cache_rs64()
2884 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, in gfx_v11_0_config_mec_cache_rs64()
2891 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2893 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); in gfx_v11_0_config_mec_cache_rs64()
2897 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2910 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2912 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); in gfx_v11_0_config_mec_cache_rs64()
2916 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2948 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, in gfx_v11_0_config_gfx_rs64()
2951 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, in gfx_v11_0_config_gfx_rs64()
2957 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_gfx_rs64()
2960 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2965 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2970 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, in gfx_v11_0_config_gfx_rs64()
2973 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, in gfx_v11_0_config_gfx_rs64()
2979 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_gfx_rs64()
2982 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2987 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2992 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, in gfx_v11_0_config_gfx_rs64()
2995 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, in gfx_v11_0_config_gfx_rs64()
3001 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v11_0_config_gfx_rs64()
3006 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
3013 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
3024 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); in gfx_v11_0_wait_for_rlc_autoload_complete()
3034 bootload_status = RREG32_SOC15(GC, 0, in gfx_v11_0_wait_for_rlc_autoload_complete()
3037 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); in gfx_v11_0_wait_for_rlc_autoload_complete()
3100 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_cp_gfx_enable()
3104 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_cp_gfx_enable()
3107 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) in gfx_v11_0_cp_gfx_enable()
3152 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode()
3155 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA, in gfx_v11_0_cp_gfx_load_pfp_microcode()
3158 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); in gfx_v11_0_cp_gfx_load_pfp_microcode()
3224 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3226 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3229 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3233 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3241 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3254 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3256 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3259 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3274 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3277 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3284 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3291 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3300 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3302 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3304 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3310 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3313 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3316 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3318 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3321 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3370 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0); in gfx_v11_0_cp_gfx_load_me_microcode()
3373 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA, in gfx_v11_0_cp_gfx_load_me_microcode()
3376 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); in gfx_v11_0_cp_gfx_load_me_microcode()
3442 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3444 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3447 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3451 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3459 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3472 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3474 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3478 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3493 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3496 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3503 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3510 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3519 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3521 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3523 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3529 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3532 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3535 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3537 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3540 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3594 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, in gfx_v11_0_cp_gfx_start()
3596 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); in gfx_v11_0_cp_gfx_start()
3630 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; in gfx_v11_0_cp_gfx_start()
3666 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); in gfx_v11_0_cp_gfx_switch_pipe()
3669 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); in gfx_v11_0_cp_gfx_switch_pipe()
3677 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); in gfx_v11_0_cp_gfx_set_doorbell()
3687 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); in gfx_v11_0_cp_gfx_set_doorbell()
3691 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); in gfx_v11_0_cp_gfx_set_doorbell()
3693 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, in gfx_v11_0_cp_gfx_set_doorbell()
3705 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); in gfx_v11_0_cp_gfx_resume()
3708 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); in gfx_v11_0_cp_gfx_resume()
3719 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); in gfx_v11_0_cp_gfx_resume()
3723 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v11_0_cp_gfx_resume()
3724 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); in gfx_v11_0_cp_gfx_resume()
3728 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); in gfx_v11_0_cp_gfx_resume()
3729 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & in gfx_v11_0_cp_gfx_resume()
3733 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, in gfx_v11_0_cp_gfx_resume()
3735 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, in gfx_v11_0_cp_gfx_resume()
3739 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); in gfx_v11_0_cp_gfx_resume()
3742 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); in gfx_v11_0_cp_gfx_resume()
3743 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); in gfx_v11_0_cp_gfx_resume()
3745 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); in gfx_v11_0_cp_gfx_resume()
3759 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); in gfx_v11_0_cp_gfx_resume()
3762 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr)); in gfx_v11_0_cp_gfx_resume()
3763 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); in gfx_v11_0_cp_gfx_resume()
3766 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); in gfx_v11_0_cp_gfx_resume()
3767 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & in gfx_v11_0_cp_gfx_resume()
3770 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, in gfx_v11_0_cp_gfx_resume()
3772 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, in gfx_v11_0_cp_gfx_resume()
3776 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); in gfx_v11_0_cp_gfx_resume()
3779 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr); in gfx_v11_0_cp_gfx_resume()
3780 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr)); in gfx_v11_0_cp_gfx_resume()
3781 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1); in gfx_v11_0_cp_gfx_resume()
3802 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v11_0_cp_compute_enable()
3823 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); in gfx_v11_0_cp_compute_enable()
3825 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); in gfx_v11_0_cp_compute_enable()
3836 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data); in gfx_v11_0_cp_compute_enable()
3882 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0); in gfx_v11_0_cp_compute_load_microcode()
3885 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA, in gfx_v11_0_cp_compute_load_microcode()
3888 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); in gfx_v11_0_cp_compute_load_microcode()
3952 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3956 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v11_0_cp_compute_load_microcode_rs64()
3958 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3961 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); in gfx_v11_0_cp_compute_load_microcode_rs64()
3967 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr); in gfx_v11_0_cp_compute_load_microcode_rs64()
3968 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, in gfx_v11_0_cp_compute_load_microcode_rs64()
3971 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, in gfx_v11_0_cp_compute_load_microcode_rs64()
3974 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, in gfx_v11_0_cp_compute_load_microcode_rs64()
3977 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); in gfx_v11_0_cp_compute_load_microcode_rs64()
3978 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, in gfx_v11_0_cp_compute_load_microcode_rs64()
3985 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3987 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); in gfx_v11_0_cp_compute_load_microcode_rs64()
3991 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
4004 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
4006 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); in gfx_v11_0_cp_compute_load_microcode_rs64()
4010 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
4031 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); in gfx_v11_0_kiq_setting()
4034 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); in gfx_v11_0_kiq_setting()
4040 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, in gfx_v11_0_cp_set_doorbell_range()
4042 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, in gfx_v11_0_cp_set_doorbell_range()
4046 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, in gfx_v11_0_cp_set_doorbell_range()
4048 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, in gfx_v11_0_cp_set_doorbell_range()
4354 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); in gfx_v11_0_kiq_init_register()
4357 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v11_0_kiq_init_register()
4360 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, in gfx_v11_0_kiq_init_register()
4362 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, in gfx_v11_0_kiq_init_register()
4366 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, in gfx_v11_0_kiq_init_register()
4370 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v11_0_kiq_init_register()
4374 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { in gfx_v11_0_kiq_init_register()
4375 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v11_0_kiq_init_register()
4377 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in gfx_v11_0_kiq_init_register()
4381 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, in gfx_v11_0_kiq_init_register()
4383 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, in gfx_v11_0_kiq_init_register()
4385 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, in gfx_v11_0_kiq_init_register()
4387 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, in gfx_v11_0_kiq_init_register()
4392 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, in gfx_v11_0_kiq_init_register()
4394 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, in gfx_v11_0_kiq_init_register()
4398 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, in gfx_v11_0_kiq_init_register()
4402 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, in gfx_v11_0_kiq_init_register()
4404 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, in gfx_v11_0_kiq_init_register()
4408 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, in gfx_v11_0_kiq_init_register()
4412 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, in gfx_v11_0_kiq_init_register()
4414 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, in gfx_v11_0_kiq_init_register()
4418 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, in gfx_v11_0_kiq_init_register()
4420 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, in gfx_v11_0_kiq_init_register()
4425 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, in gfx_v11_0_kiq_init_register()
4427 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, in gfx_v11_0_kiq_init_register()
4431 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v11_0_kiq_init_register()
4435 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, in gfx_v11_0_kiq_init_register()
4437 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, in gfx_v11_0_kiq_init_register()
4441 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); in gfx_v11_0_kiq_init_register()
4443 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, in gfx_v11_0_kiq_init_register()
4447 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, in gfx_v11_0_kiq_init_register()
4451 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); in gfx_v11_0_kiq_init_register()
4659 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL); in gfx_v11_0_select_cp_fw_arch()
4661 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp); in gfx_v11_0_select_cp_fw_arch()
4663 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL); in gfx_v11_0_select_cp_fw_arch()
4665 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp); in gfx_v11_0_select_cp_fw_arch()
4676 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); in get_gb_addr_config()
4712 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); in gfx_v11_0_disable_gpa_mode()
4714 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); in gfx_v11_0_disable_gpa_mode()
4716 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); in gfx_v11_0_disable_gpa_mode()
4718 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); in gfx_v11_0_disable_gpa_mode()
4816 adev->gfx.imu_fw_version = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_0); in gfx_v11_0_hw_init()
4920 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), in gfx_v11_0_is_idle()
4935 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & in gfx_v11_0_wait_for_idle()
4954 WREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX, tmp); in gfx_v11_0_request_gfx_index_mutex()
4956 val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX); in gfx_v11_0_request_gfx_index_mutex()
4986 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); in gfx_v11_0_soft_reset()
4991 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); in gfx_v11_0_soft_reset()
4999 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); in gfx_v11_0_soft_reset()
5000 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); in gfx_v11_0_soft_reset()
5009 WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1); in gfx_v11_0_soft_reset()
5025 WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe); in gfx_v11_0_soft_reset()
5029 RREG32_SOC15(GC, 0, regCP_VMID_RESET); in gfx_v11_0_soft_reset()
5030 RREG32_SOC15(GC, 0, regCP_VMID_RESET); in gfx_v11_0_soft_reset()
5031 RREG32_SOC15(GC, 0, regCP_VMID_RESET); in gfx_v11_0_soft_reset()
5042 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) && in gfx_v11_0_soft_reset()
5043 !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE)) in gfx_v11_0_soft_reset()
5053 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); in gfx_v11_0_soft_reset()
5064 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); in gfx_v11_0_soft_reset()
5066 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); in gfx_v11_0_soft_reset()
5077 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); in gfx_v11_0_soft_reset()
5079 tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL); in gfx_v11_0_soft_reset()
5081 WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp); in gfx_v11_0_soft_reset()
5083 WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0); in gfx_v11_0_soft_reset()
5084 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0); in gfx_v11_0_soft_reset()
5087 if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET)) in gfx_v11_0_soft_reset()
5096 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); in gfx_v11_0_soft_reset()
5101 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); in gfx_v11_0_soft_reset()
5149 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); in gfx_v11_0_get_gpu_clock_counter()
5150 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); in gfx_v11_0_get_gpu_clock_counter()
5151 clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); in gfx_v11_0_get_gpu_clock_counter()
5153 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); in gfx_v11_0_get_gpu_clock_counter()
5180 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid, in gfx_v11_0_ring_emit_gds_switch()
5185 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid, in gfx_v11_0_ring_emit_gds_switch()
5190 SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid, in gfx_v11_0_ring_emit_gds_switch()
5195 SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid, in gfx_v11_0_ring_emit_gds_switch()
5276 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); in gfx_v11_0_is_rlc_enabled()
5288 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); in gfx_v11_0_set_safe_mode()
5292 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), in gfx_v11_0_set_safe_mode()
5301 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); in gfx_v11_0_unset_safe_mode()
5312 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_update_perf_clk()
5320 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v11_0_update_perf_clk()
5331 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_update_sram_fgcg()
5339 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v11_0_update_sram_fgcg()
5350 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_update_repeater_fgcg()
5358 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v11_0_update_repeater_fgcg()
5373 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_update_medium_grain_clock_gating()
5380 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v11_0_update_medium_grain_clock_gating()
5384 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_update_medium_grain_clock_gating()
5391 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v11_0_update_medium_grain_clock_gating()
5409 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_update_coarse_grain_clock_gating()
5422 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5425 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5440 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5443 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); in gfx_v11_0_update_coarse_grain_clock_gating()
5458 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5461 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); in gfx_v11_0_update_coarse_grain_clock_gating()
5468 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5470 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); in gfx_v11_0_update_coarse_grain_clock_gating()
5475 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5477 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5479 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5483 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5485 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5489 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5498 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5501 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); in gfx_v11_0_update_coarse_grain_clock_gating()
5509 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5511 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5513 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5517 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5519 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5557 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); in gfx_v11_0_update_spm_vmid()
5568 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); in gfx_v11_0_update_spm_vmid()
5570 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); in gfx_v11_0_update_spm_vmid()
5599 u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); in gfx_v11_cntl_power_gating()
5606 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data); in gfx_v11_cntl_power_gating()
5617 WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1); in gfx_v11_cntl_power_gating()
5705 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_get_clockgating_state()
5722 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v11_0_get_clockgating_state()
5731 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); in gfx_v11_0_get_clockgating_state()
5755 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); in gfx_v11_0_ring_get_wptr_gfx()
5756 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; in gfx_v11_0_ring_get_wptr_gfx()
5772 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, in gfx_v11_0_ring_set_wptr_gfx()
5774 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, in gfx_v11_0_ring_set_wptr_gfx()
6006 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); in gfx_v11_0_ring_emit_fence_kiq()
6301 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); in gfx_v11_0_set_gfx_eop_interrupt_state()
6304 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); in gfx_v11_0_set_gfx_eop_interrupt_state()
6317 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v11_0_set_gfx_eop_interrupt_state()
6322 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_gfx_eop_interrupt_state()
6325 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v11_0_set_gfx_eop_interrupt_state()
6330 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_gfx_eop_interrupt_state()
6352 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
6355 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
6358 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
6361 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
6374 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v11_0_set_compute_eop_interrupt_state()
6379 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v11_0_set_compute_eop_interrupt_state()
6382 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v11_0_set_compute_eop_interrupt_state()
6387 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v11_0_set_compute_eop_interrupt_state()
6493 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v11_0_set_priv_reg_fault_state()
6497 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_priv_reg_fault_state()
6507 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v11_0_set_priv_reg_fault_state()
6511 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_priv_reg_fault_state()
6539 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v11_0_set_bad_op_fault_state()
6543 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_bad_op_fault_state()
6553 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v11_0_set_bad_op_fault_state()
6557 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_bad_op_fault_state()
6584 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v11_0_set_priv_inst_fault_state()
6588 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_priv_inst_fault_state()
6683 target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
6689 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);
6692 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp);
6694 tmp = RREG32_SOC15_IP(GC, target);
6697 WREG32_SOC15_IP(GC, target, tmp);
6699 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);
6702 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp);
6704 tmp = RREG32_SOC15_IP(GC, target);
6707 WREG32_SOC15_IP(GC, target, tmp);
6787 WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe); in gfx_v11_reset_gfx_pipe()
6788 WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe); in gfx_v11_reset_gfx_pipe()
6790 r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) - in gfx_v11_reset_gfx_pipe()
6851 reset_pipe = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v11_0_reset_compute_pipe()
6884 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_pipe); in gfx_v11_0_reset_compute_pipe()
6885 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_pipe); in gfx_v11_0_reset_compute_pipe()
6886 r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) - in gfx_v11_0_reset_compute_pipe()
6950 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_pipe); in gfx_v11_0_reset_compute_pipe()
6951 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_pipe); in gfx_v11_0_reset_compute_pipe()
6952 r = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_MEC1_INSTR_PNTR)); in gfx_v11_0_reset_compute_pipe()
7098 RREG32(SOC15_REG_OFFSET(GC, 0, in gfx_v11_ip_dump()
7416 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); in gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh()
7422 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); in gfx_v11_0_get_wgp_active_bitmap_per_sh()
7423 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); in gfx_v11_0_get_wgp_active_bitmap_per_sh()