Lines Matching refs:me
372 uint32_t me = 0, eng_sel = 0; in gfx11_kiq_map_queues() local
376 me = 1; in gfx11_kiq_map_queues()
380 me = 0; in gfx11_kiq_map_queues()
384 me = 2; in gfx11_kiq_map_queues()
398 PACKET3_MAP_QUEUES_ME((me)) | in gfx11_kiq_map_queues()
935 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); in gfx_v11_0_me_init()
1042 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) in gfx_v11_0_select_me_pipe_q() argument
1044 soc21_grbm_select(adev, me, pipe, q, vm); in gfx_v11_0_select_me_pipe_q()
1126 int me, int pipe, int queue) in gfx_v11_0_gfx_ring_init() argument
1134 ring->me = me; in gfx_v11_0_gfx_ring_init()
1150 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); in gfx_v11_0_gfx_ring_init()
1170 ring->me = mec + 1; in gfx_v11_0_compute_ring_init()
1180 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); in gfx_v11_0_compute_ring_init()
1183 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) in gfx_v11_0_compute_ring_init()
1562 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * in gfx_v11_0_alloc_ip_dump()
1563 adev->gfx.me.num_queue_per_pipe; in gfx_v11_0_alloc_ip_dump()
1593 adev->gfx.me.num_me = 1; in gfx_v11_0_sw_init()
1594 adev->gfx.me.num_pipe_per_me = 1; in gfx_v11_0_sw_init()
1595 adev->gfx.me.num_queue_per_pipe = 2; in gfx_v11_0_sw_init()
1601 adev->gfx.me.num_me = 1; in gfx_v11_0_sw_init()
1602 adev->gfx.me.num_pipe_per_me = 1; in gfx_v11_0_sw_init()
1603 adev->gfx.me.num_queue_per_pipe = 1; in gfx_v11_0_sw_init()
1763 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_0_sw_init()
1765 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { in gfx_v11_0_sw_init()
1877 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, in gfx_v11_0_me_fini()
1878 &adev->gfx.me.me_fw_gpu_addr, in gfx_v11_0_me_fini()
1879 (void **)&adev->gfx.me.me_fw_ptr); in gfx_v11_0_me_fini()
1881 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, in gfx_v11_0_me_fini()
1882 &adev->gfx.me.me_fw_data_gpu_addr, in gfx_v11_0_me_fini()
1883 (void **)&adev->gfx.me.me_fw_data_ptr); in gfx_v11_0_me_fini()
2149 int me, int pipe) in gfx_v11_0_get_cpg_int_cntl() argument
2151 if (me != 0) in gfx_v11_0_get_cpg_int_cntl()
2165 int me, int pipe) in gfx_v11_0_get_cpc_int_cntl() argument
2172 if (me != 1) in gfx_v11_0_get_cpc_int_cntl()
2198 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_0_enable_gui_idle_interrupt()
2199 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_0_enable_gui_idle_interrupt()
2661 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { in gfx_v11_0_config_pfp_cache_rs64()
2784 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { in gfx_v11_0_config_me_cache_rs64()
3272 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3354 &adev->gfx.me.me_fw_obj, in gfx_v11_0_cp_gfx_load_me_microcode()
3355 &adev->gfx.me.me_fw_gpu_addr, in gfx_v11_0_cp_gfx_load_me_microcode()
3356 (void **)&adev->gfx.me.me_fw_ptr); in gfx_v11_0_cp_gfx_load_me_microcode()
3363 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); in gfx_v11_0_cp_gfx_load_me_microcode()
3365 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); in gfx_v11_0_cp_gfx_load_me_microcode()
3366 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); in gfx_v11_0_cp_gfx_load_me_microcode()
3368 gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr); in gfx_v11_0_cp_gfx_load_me_microcode()
3409 &adev->gfx.me.me_fw_obj, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3410 &adev->gfx.me.me_fw_gpu_addr, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3411 (void **)&adev->gfx.me.me_fw_ptr); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3422 &adev->gfx.me.me_fw_data_obj, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3423 &adev->gfx.me.me_fw_data_gpu_addr, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3424 (void **)&adev->gfx.me.me_fw_data_ptr); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3431 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3432 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3434 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3435 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3436 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3437 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3443 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3445 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3491 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3522 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3524 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
4033 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); in gfx_v11_0_kiq_setting()
4174 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v11_0_kgq_init_queue()
4178 if (adev->gfx.me.mqd_backup[mqd_idx]) in gfx_v11_0_kgq_init_queue()
4179 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v11_0_kgq_init_queue()
4182 if (adev->gfx.me.mqd_backup[mqd_idx]) in gfx_v11_0_kgq_init_queue()
4183 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v11_0_kgq_init_queue()
4473 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v11_0_kiq_init_queue()
4482 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v11_0_kiq_init_queue()
4504 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v11_0_kcq_init_queue()
4828 for (m = 0; m < adev->gfx.me.num_me; m++) { in gfx_v11_0_set_userq_eop_interrupts()
4829 for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) { in gfx_v11_0_set_userq_eop_interrupts()
5004 for (i = 0; i < adev->gfx.me.num_me; ++i) { in gfx_v11_0_soft_reset()
5005 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { in gfx_v11_0_soft_reset()
5006 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { in gfx_v11_0_soft_reset()
5818 switch (ring->me) { in gfx_v11_0_ring_emit_hdp_flush()
6293 uint32_t me, uint32_t pipe, in gfx_v11_0_set_gfx_eop_interrupt_state() argument
6298 if (!me) { in gfx_v11_0_set_gfx_eop_interrupt_state()
6311 DRM_DEBUG("invalid me %d\n", me); in gfx_v11_0_set_gfx_eop_interrupt_state()
6338 int me, int pipe, in gfx_v11_0_set_compute_eop_interrupt_state() argument
6349 if (me == 1) { in gfx_v11_0_set_compute_eop_interrupt_state()
6368 DRM_DEBUG("invalid me %d\n", me); in gfx_v11_0_set_compute_eop_interrupt_state()
6465 if ((ring->me == me_id) && in gfx_v11_0_eop_irq()
6488 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_0_set_priv_reg_fault_state()
6489 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_0_set_priv_reg_fault_state()
6534 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_0_set_bad_op_fault_state()
6535 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_0_set_bad_op_fault_state()
6579 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_0_set_priv_inst_fault_state()
6580 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_0_set_priv_inst_fault_state()
6616 if (ring->me == me_id && ring->pipe == pipe_id && in gfx_v11_0_handle_priv_fault()
6625 if (ring->me == me_id && ring->pipe == pipe_id && in gfx_v11_0_handle_priv_fault()
6760 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v11_reset_gfx_pipe()
6849 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v11_0_reset_compute_pipe()
6889 if (ring->me == 1) { in gfx_v11_0_reset_compute_pipe()
7048 adev->gfx.me.num_me, in gfx_v11_ip_print()
7049 adev->gfx.me.num_pipe_per_me, in gfx_v11_ip_print()
7050 adev->gfx.me.num_queue_per_pipe); in gfx_v11_ip_print()
7052 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_ip_print()
7053 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_ip_print()
7054 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { in gfx_v11_ip_print()
7092 soc21_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); in gfx_v11_ip_dump()
7121 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_ip_dump()
7122 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_ip_dump()
7123 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { in gfx_v11_ip_dump()