Lines Matching refs:mec
928 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); in gfx_v11_0_mec_fini()
929 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); in gfx_v11_0_mec_fini()
930 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); in gfx_v11_0_mec_fini()
955 &adev->gfx.mec.hpd_eop_obj, in gfx_v11_0_mec_init()
956 &adev->gfx.mec.hpd_eop_gpu_addr, in gfx_v11_0_mec_init()
966 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); in gfx_v11_0_mec_init()
967 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v11_0_mec_init()
1160 int mec, int pipe, int queue) in gfx_v11_0_compute_ring_init() argument
1170 ring->me = mec + 1; in gfx_v11_0_compute_ring_init()
1177 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr in gfx_v11_0_compute_ring_init()
1183 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) in gfx_v11_0_compute_ring_init()
1549 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v11_0_alloc_ip_dump()
1550 adev->gfx.mec.num_queue_per_pipe; in gfx_v11_0_alloc_ip_dump()
1596 adev->gfx.mec.num_mec = 1; in gfx_v11_0_sw_init()
1597 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v11_0_sw_init()
1598 adev->gfx.mec.num_queue_per_pipe = 4; in gfx_v11_0_sw_init()
1604 adev->gfx.mec.num_mec = 1; in gfx_v11_0_sw_init()
1605 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v11_0_sw_init()
1606 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v11_0_sw_init()
1782 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v11_0_sw_init()
1783 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v11_0_sw_init()
1784 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v11_0_sw_init()
2870 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { in gfx_v11_0_config_mec_cache_rs64()
3865 &adev->gfx.mec.mec_fw_obj, in gfx_v11_0_cp_compute_load_microcode()
3866 &adev->gfx.mec.mec_fw_gpu_addr, in gfx_v11_0_cp_compute_load_microcode()
3876 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); in gfx_v11_0_cp_compute_load_microcode()
3877 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); in gfx_v11_0_cp_compute_load_microcode()
3879 gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr); in gfx_v11_0_cp_compute_load_microcode()
3922 &adev->gfx.mec.mec_fw_obj, in gfx_v11_0_cp_compute_load_microcode_rs64()
3923 &adev->gfx.mec.mec_fw_gpu_addr, in gfx_v11_0_cp_compute_load_microcode_rs64()
3935 &adev->gfx.mec.mec_fw_data_obj, in gfx_v11_0_cp_compute_load_microcode_rs64()
3936 &adev->gfx.mec.mec_fw_data_gpu_addr, in gfx_v11_0_cp_compute_load_microcode_rs64()
3947 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); in gfx_v11_0_cp_compute_load_microcode_rs64()
3948 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); in gfx_v11_0_cp_compute_load_microcode_rs64()
3949 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); in gfx_v11_0_cp_compute_load_microcode_rs64()
3950 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); in gfx_v11_0_cp_compute_load_microcode_rs64()
3964 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { in gfx_v11_0_cp_compute_load_microcode_rs64()
3967 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr); in gfx_v11_0_cp_compute_load_microcode_rs64()
3969 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr)); in gfx_v11_0_cp_compute_load_microcode_rs64()
3977 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); in gfx_v11_0_cp_compute_load_microcode_rs64()
3979 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); in gfx_v11_0_cp_compute_load_microcode_rs64()
4509 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v11_0_kcq_init_queue()
4510 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v11_0_kcq_init_queue()
4513 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v11_0_kcq_init_queue()
4514 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v11_0_kcq_init_queue()
4844 for (m = 0; m < adev->gfx.mec.num_mec; ++m) { in gfx_v11_0_set_userq_eop_interrupts()
4845 for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) { in gfx_v11_0_set_userq_eop_interrupts()
4847 + (m * adev->gfx.mec.num_pipe_per_mec) in gfx_v11_0_set_userq_eop_interrupts()
4994 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v11_0_soft_reset()
4995 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v11_0_soft_reset()
4996 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v11_0_soft_reset()
6501 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v11_0_set_priv_reg_fault_state()
6502 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v11_0_set_priv_reg_fault_state()
6547 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v11_0_set_bad_op_fault_state()
6548 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v11_0_set_bad_op_fault_state()
7018 adev->gfx.mec.num_mec, in gfx_v11_ip_print()
7019 adev->gfx.mec.num_pipe_per_mec, in gfx_v11_ip_print()
7020 adev->gfx.mec.num_queue_per_pipe); in gfx_v11_ip_print()
7022 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v11_ip_print()
7023 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v11_ip_print()
7024 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v11_ip_print()
7088 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v11_ip_dump()
7089 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v11_ip_dump()
7090 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v11_ip_dump()