Lines Matching refs:mqd
4053 struct v11_gfx_mqd *mqd, in gfx_v11_0_gfx_mqd_set_priority() argument
4067 mqd->cp_gfx_hqd_queue_priority = tmp; in gfx_v11_0_gfx_mqd_set_priority()
4073 struct v11_gfx_mqd *mqd = m; in gfx_v11_0_gfx_mqd_init() local
4079 mqd->cp_gfx_hqd_wptr = 0; in gfx_v11_0_gfx_mqd_init()
4080 mqd->cp_gfx_hqd_wptr_hi = 0; in gfx_v11_0_gfx_mqd_init()
4083 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; in gfx_v11_0_gfx_mqd_init()
4084 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); in gfx_v11_0_gfx_mqd_init()
4091 mqd->cp_gfx_mqd_control = tmp; in gfx_v11_0_gfx_mqd_init()
4096 mqd->cp_gfx_hqd_vmid = 0; in gfx_v11_0_gfx_mqd_init()
4099 gfx_v11_0_gfx_mqd_set_priority(adev, mqd, prop); in gfx_v11_0_gfx_mqd_init()
4104 mqd->cp_gfx_hqd_quantum = tmp; in gfx_v11_0_gfx_mqd_init()
4108 mqd->cp_gfx_hqd_base = hqd_gpu_addr; in gfx_v11_0_gfx_mqd_init()
4109 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); in gfx_v11_0_gfx_mqd_init()
4113 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; in gfx_v11_0_gfx_mqd_init()
4114 mqd->cp_gfx_hqd_rptr_addr_hi = in gfx_v11_0_gfx_mqd_init()
4119 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v11_0_gfx_mqd_init()
4120 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v11_0_gfx_mqd_init()
4132 mqd->cp_gfx_hqd_cntl = tmp; in gfx_v11_0_gfx_mqd_init()
4144 mqd->cp_rb_doorbell_control = tmp; in gfx_v11_0_gfx_mqd_init()
4147 mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT; in gfx_v11_0_gfx_mqd_init()
4150 mqd->cp_gfx_hqd_active = 1; in gfx_v11_0_gfx_mqd_init()
4153 mqd->shadow_base_lo = lower_32_bits(prop->shadow_addr); in gfx_v11_0_gfx_mqd_init()
4154 mqd->shadow_base_hi = upper_32_bits(prop->shadow_addr); in gfx_v11_0_gfx_mqd_init()
4155 mqd->gds_bkup_base_lo = lower_32_bits(prop->gds_bkup_addr); in gfx_v11_0_gfx_mqd_init()
4156 mqd->gds_bkup_base_hi = upper_32_bits(prop->gds_bkup_addr); in gfx_v11_0_gfx_mqd_init()
4157 mqd->fw_work_area_base_lo = lower_32_bits(prop->csa_addr); in gfx_v11_0_gfx_mqd_init()
4158 mqd->fw_work_area_base_hi = upper_32_bits(prop->csa_addr); in gfx_v11_0_gfx_mqd_init()
4159 mqd->fence_address_lo = lower_32_bits(prop->fence_address); in gfx_v11_0_gfx_mqd_init()
4160 mqd->fence_address_hi = upper_32_bits(prop->fence_address); in gfx_v11_0_gfx_mqd_init()
4168 struct v11_gfx_mqd *mqd = ring->mqd_ptr; in gfx_v11_0_kgq_init_queue() local
4172 memset((void *)mqd, 0, sizeof(*mqd)); in gfx_v11_0_kgq_init_queue()
4179 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v11_0_kgq_init_queue()
4183 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v11_0_kgq_init_queue()
4213 struct v11_compute_mqd *mqd = m; in gfx_v11_0_compute_mqd_init() local
4217 mqd->header = 0xC0310800; in gfx_v11_0_compute_mqd_init()
4218 mqd->compute_pipelinestat_enable = 0x00000001; in gfx_v11_0_compute_mqd_init()
4219 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; in gfx_v11_0_compute_mqd_init()
4220 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; in gfx_v11_0_compute_mqd_init()
4221 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; in gfx_v11_0_compute_mqd_init()
4222 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; in gfx_v11_0_compute_mqd_init()
4223 mqd->compute_misc_reserved = 0x00000007; in gfx_v11_0_compute_mqd_init()
4226 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; in gfx_v11_0_compute_mqd_init()
4227 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); in gfx_v11_0_compute_mqd_init()
4234 mqd->cp_hqd_eop_control = tmp; in gfx_v11_0_compute_mqd_init()
4253 mqd->cp_hqd_pq_doorbell_control = tmp; in gfx_v11_0_compute_mqd_init()
4256 mqd->cp_hqd_dequeue_request = 0; in gfx_v11_0_compute_mqd_init()
4257 mqd->cp_hqd_pq_rptr = 0; in gfx_v11_0_compute_mqd_init()
4258 mqd->cp_hqd_pq_wptr_lo = 0; in gfx_v11_0_compute_mqd_init()
4259 mqd->cp_hqd_pq_wptr_hi = 0; in gfx_v11_0_compute_mqd_init()
4262 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; in gfx_v11_0_compute_mqd_init()
4263 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); in gfx_v11_0_compute_mqd_init()
4268 mqd->cp_mqd_control = tmp; in gfx_v11_0_compute_mqd_init()
4272 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; in gfx_v11_0_compute_mqd_init()
4273 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in gfx_v11_0_compute_mqd_init()
4288 mqd->cp_hqd_pq_control = tmp; in gfx_v11_0_compute_mqd_init()
4292 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v11_0_compute_mqd_init()
4293 mqd->cp_hqd_pq_rptr_report_addr_hi = in gfx_v11_0_compute_mqd_init()
4298 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v11_0_compute_mqd_init()
4299 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v11_0_compute_mqd_init()
4316 mqd->cp_hqd_pq_doorbell_control = tmp; in gfx_v11_0_compute_mqd_init()
4319 mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT; in gfx_v11_0_compute_mqd_init()
4322 mqd->cp_hqd_vmid = 0; in gfx_v11_0_compute_mqd_init()
4326 mqd->cp_hqd_persistent_state = tmp; in gfx_v11_0_compute_mqd_init()
4331 mqd->cp_hqd_ib_control = tmp; in gfx_v11_0_compute_mqd_init()
4334 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; in gfx_v11_0_compute_mqd_init()
4335 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; in gfx_v11_0_compute_mqd_init()
4337 mqd->cp_hqd_active = prop->hqd_active; in gfx_v11_0_compute_mqd_init()
4340 mqd->fence_address_lo = lower_32_bits(prop->fence_address); in gfx_v11_0_compute_mqd_init()
4341 mqd->fence_address_hi = upper_32_bits(prop->fence_address); in gfx_v11_0_compute_mqd_init()
4349 struct v11_compute_mqd *mqd = ring->mqd_ptr; in gfx_v11_0_kiq_init_register() local
4361 mqd->cp_hqd_eop_base_addr_lo); in gfx_v11_0_kiq_init_register()
4363 mqd->cp_hqd_eop_base_addr_hi); in gfx_v11_0_kiq_init_register()
4367 mqd->cp_hqd_eop_control); in gfx_v11_0_kiq_init_register()
4371 mqd->cp_hqd_pq_doorbell_control); in gfx_v11_0_kiq_init_register()
4382 mqd->cp_hqd_dequeue_request); in gfx_v11_0_kiq_init_register()
4384 mqd->cp_hqd_pq_rptr); in gfx_v11_0_kiq_init_register()
4386 mqd->cp_hqd_pq_wptr_lo); in gfx_v11_0_kiq_init_register()
4388 mqd->cp_hqd_pq_wptr_hi); in gfx_v11_0_kiq_init_register()
4393 mqd->cp_mqd_base_addr_lo); in gfx_v11_0_kiq_init_register()
4395 mqd->cp_mqd_base_addr_hi); in gfx_v11_0_kiq_init_register()
4399 mqd->cp_mqd_control); in gfx_v11_0_kiq_init_register()
4403 mqd->cp_hqd_pq_base_lo); in gfx_v11_0_kiq_init_register()
4405 mqd->cp_hqd_pq_base_hi); in gfx_v11_0_kiq_init_register()
4409 mqd->cp_hqd_pq_control); in gfx_v11_0_kiq_init_register()
4413 mqd->cp_hqd_pq_rptr_report_addr_lo); in gfx_v11_0_kiq_init_register()
4415 mqd->cp_hqd_pq_rptr_report_addr_hi); in gfx_v11_0_kiq_init_register()
4419 mqd->cp_hqd_pq_wptr_poll_addr_lo); in gfx_v11_0_kiq_init_register()
4421 mqd->cp_hqd_pq_wptr_poll_addr_hi); in gfx_v11_0_kiq_init_register()
4432 mqd->cp_hqd_pq_doorbell_control); in gfx_v11_0_kiq_init_register()
4436 mqd->cp_hqd_pq_wptr_lo); in gfx_v11_0_kiq_init_register()
4438 mqd->cp_hqd_pq_wptr_hi); in gfx_v11_0_kiq_init_register()
4441 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); in gfx_v11_0_kiq_init_register()
4444 mqd->cp_hqd_persistent_state); in gfx_v11_0_kiq_init_register()
4448 mqd->cp_hqd_active); in gfx_v11_0_kiq_init_register()
4459 struct v11_compute_mqd *mqd = ring->mqd_ptr; in gfx_v11_0_kiq_init_queue() local
4466 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); in gfx_v11_0_kiq_init_queue()
4478 memset((void *)mqd, 0, sizeof(*mqd)); in gfx_v11_0_kiq_init_queue()
4489 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); in gfx_v11_0_kiq_init_queue()
4498 struct v11_compute_mqd *mqd = ring->mqd_ptr; in gfx_v11_0_kcq_init_queue() local
4502 memset((void *)mqd, 0, sizeof(*mqd)); in gfx_v11_0_kcq_init_queue()
4510 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v11_0_kcq_init_queue()
4514 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v11_0_kcq_init_queue()