Lines Matching refs:GC
86 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),
87 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),
88 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3),
89 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1),
90 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2),
91 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3),
92 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1),
93 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1),
94 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT),
95 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT),
96 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT),
97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2),
98 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2),
99 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS),
100 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR),
101 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0),
102 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE),
103 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
104 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR),
105 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE),
106 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR),
107 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR),
108 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
109 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ),
110 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
111 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
112 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),
113 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO),
114 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI),
115 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ),
116 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS),
117 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS),
118 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS),
119 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS),
120 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2),
121 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS),
122 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS),
123 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES),
124 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS),
125 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS),
126 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL),
127 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32),
128 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32),
129 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),
130 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),
131 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL),
132 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR),
133 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR),
134 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR),
135 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS),
136 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0),
137 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1),
138 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR),
140 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
141 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
142 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
143 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
144 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
145 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
146 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
147 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
149 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0),
150 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1),
151 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2),
152 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3)
157 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID),
158 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE),
159 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY),
160 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY),
161 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM),
162 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE),
163 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI),
164 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR),
165 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR),
166 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI),
167 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),
168 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL),
169 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR),
170 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI),
171 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR),
172 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL),
173 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST),
174 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR),
175 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI),
176 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL),
177 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR),
178 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR),
179 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS),
180 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO),
181 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI),
182 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL),
183 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET),
184 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE),
185 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET),
186 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE),
187 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE),
188 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR),
189 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM),
190 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO),
191 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI),
192 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
193 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
194 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET),
195 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS),
197 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
198 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
199 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
200 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
201 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
202 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
203 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
204 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
209 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE),
210 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID),
211 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY),
212 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM),
213 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE),
214 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI),
215 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET),
216 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL),
217 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR),
218 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR),
219 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI),
220 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST),
221 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED),
222 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL),
223 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0),
224 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0),
225 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR),
226 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI),
227 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO),
228 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI),
229 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
230 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
231 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
232 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
233 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),
235 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
236 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
237 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
238 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
239 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
240 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
241 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
242 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
243 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
244 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
245 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
246 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
247 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
248 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
249 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
250 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
254 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f),
255 SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000),
256 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020)
260 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x00008000, 0x00008000),
454 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); in gfx_v12_0_ring_test_ring()
737 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); in gfx_v12_0_init_rlcg_reg_access_ctrl()
738 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); in gfx_v12_0_init_rlcg_reg_access_ctrl()
739 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); in gfx_v12_0_init_rlcg_reg_access_ctrl()
740 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); in gfx_v12_0_init_rlcg_reg_access_ctrl()
741 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); in gfx_v12_0_init_rlcg_reg_access_ctrl()
742 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); in gfx_v12_0_init_rlcg_reg_access_ctrl()
743 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); in gfx_v12_0_init_rlcg_reg_access_ctrl()
819 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, in wave_read_ind()
822 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); in wave_read_ind()
829 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, in wave_read_regs()
835 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); in wave_read_regs()
1322 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); in gfx_v12_0_rlc_backdoor_autoload_enable()
1323 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); in gfx_v12_0_rlc_backdoor_autoload_enable()
1325 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); in gfx_v12_0_rlc_backdoor_autoload_enable()
1341 data = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); in gfx_v12_0_rlc_backdoor_autoload_enable()
1344 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, data); in gfx_v12_0_rlc_backdoor_autoload_enable()
1345 WREG32_SOC15(GC, 0, regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); in gfx_v12_0_rlc_backdoor_autoload_enable()
1686 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); in gfx_v12_0_select_se_sh()
1693 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_CC_GC_SA_UNIT_DISABLE); in gfx_v12_0_get_sa_active_bitmap()
1697 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_GC_USER_SA_UNIT_DISABLE); in gfx_v12_0_get_sa_active_bitmap()
1712 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); in gfx_v12_0_get_rb_active_bitmap()
1716 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); in gfx_v12_0_get_rb_active_bitmap()
1780 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); in gfx_v12_0_init_compute_vmid()
1781 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); in gfx_v12_0_init_compute_vmid()
1784 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); in gfx_v12_0_init_compute_vmid()
1786 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); in gfx_v12_0_init_compute_vmid()
1807 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); in gfx_v12_0_constants_init()
1820 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); in gfx_v12_0_constants_init()
1826 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); in gfx_v12_0_constants_init()
1844 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); in gfx_v12_0_get_cpg_int_cntl()
1863 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); in gfx_v12_0_get_cpc_int_cntl()
1865 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); in gfx_v12_0_get_cpc_int_cntl()
1885 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v12_0_enable_gui_idle_interrupt()
1894 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); in gfx_v12_0_enable_gui_idle_interrupt()
1904 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, in gfx_v12_0_init_csb()
1906 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, in gfx_v12_0_init_csb()
1908 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); in gfx_v12_0_init_csb()
1915 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); in gfx_v12_0_rlc_stop()
1918 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); in gfx_v12_0_rlc_stop()
1923 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v12_0_rlc_reset()
1925 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v12_0_rlc_reset()
1934 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); in gfx_v12_0_rlc_smu_handshake_cntl()
1948 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); in gfx_v12_0_rlc_smu_handshake_cntl()
1958 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v12_0_rlc_start()
1967 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); in gfx_v12_0_rlc_enable_srm()
1970 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); in gfx_v12_0_rlc_enable_srm()
1984 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, in gfx_v12_0_load_rlcg_microcode()
1988 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, in gfx_v12_0_load_rlcg_microcode()
1991 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v12_0_load_rlcg_microcode()
2007 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); in gfx_v12_0_load_rlc_iram_dram_microcode()
2012 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, in gfx_v12_0_load_rlc_iram_dram_microcode()
2016 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); in gfx_v12_0_load_rlc_iram_dram_microcode()
2022 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); in gfx_v12_0_load_rlc_iram_dram_microcode()
2026 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, in gfx_v12_0_load_rlc_iram_dram_microcode()
2030 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); in gfx_v12_0_load_rlc_iram_dram_microcode()
2032 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); in gfx_v12_0_load_rlc_iram_dram_microcode()
2035 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); in gfx_v12_0_load_rlc_iram_dram_microcode()
2084 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); in gfx_v12_0_rlc_resume()
2087 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); in gfx_v12_0_rlc_resume()
2121 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, in gfx_v12_0_config_gfx_rs64()
2124 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, in gfx_v12_0_config_gfx_rs64()
2130 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v12_0_config_gfx_rs64()
2133 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_config_gfx_rs64()
2138 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_config_gfx_rs64()
2143 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, in gfx_v12_0_config_gfx_rs64()
2146 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, in gfx_v12_0_config_gfx_rs64()
2152 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v12_0_config_gfx_rs64()
2155 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_config_gfx_rs64()
2160 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_config_gfx_rs64()
2165 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, in gfx_v12_0_config_gfx_rs64()
2168 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, in gfx_v12_0_config_gfx_rs64()
2174 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v12_0_config_gfx_rs64()
2179 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v12_0_config_gfx_rs64()
2186 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v12_0_config_gfx_rs64()
2199 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, in gfx_v12_0_set_pfp_ucode_start_addr()
2202 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, in gfx_v12_0_set_pfp_ucode_start_addr()
2209 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v12_0_set_pfp_ucode_start_addr()
2216 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_set_pfp_ucode_start_addr()
2225 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_set_pfp_ucode_start_addr()
2241 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, in gfx_v12_0_set_me_ucode_start_addr()
2244 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, in gfx_v12_0_set_me_ucode_start_addr()
2251 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v12_0_set_me_ucode_start_addr()
2258 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_set_me_ucode_start_addr()
2267 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_set_me_ucode_start_addr()
2283 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, in gfx_v12_0_set_mec_ucode_start_addr()
2286 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, in gfx_v12_0_set_mec_ucode_start_addr()
2300 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); in gfx_v12_0_wait_for_rlc_autoload_complete()
2301 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); in gfx_v12_0_wait_for_rlc_autoload_complete()
2330 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v12_0_cp_gfx_enable()
2334 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_cp_gfx_enable()
2337 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) in gfx_v12_0_cp_gfx_enable()
2405 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2407 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2410 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2414 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2422 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2435 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2437 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2440 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2456 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2458 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2464 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2467 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2470 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2472 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2475 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2549 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
2551 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
2554 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
2558 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
2566 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
2579 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
2581 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
2585 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
2601 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
2603 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
2609 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
2612 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
2615 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
2617 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
2620 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
2664 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, in gfx_v12_0_cp_gfx_start()
2666 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); in gfx_v12_0_cp_gfx_start()
2679 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); in gfx_v12_0_cp_gfx_switch_pipe()
2682 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); in gfx_v12_0_cp_gfx_switch_pipe()
2690 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); in gfx_v12_0_cp_gfx_set_doorbell()
2700 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); in gfx_v12_0_cp_gfx_set_doorbell()
2704 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); in gfx_v12_0_cp_gfx_set_doorbell()
2706 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, in gfx_v12_0_cp_gfx_set_doorbell()
2718 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); in gfx_v12_0_cp_gfx_resume()
2721 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); in gfx_v12_0_cp_gfx_resume()
2732 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); in gfx_v12_0_cp_gfx_resume()
2736 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v12_0_cp_gfx_resume()
2737 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); in gfx_v12_0_cp_gfx_resume()
2741 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); in gfx_v12_0_cp_gfx_resume()
2742 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & in gfx_v12_0_cp_gfx_resume()
2746 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, in gfx_v12_0_cp_gfx_resume()
2748 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, in gfx_v12_0_cp_gfx_resume()
2752 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); in gfx_v12_0_cp_gfx_resume()
2755 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); in gfx_v12_0_cp_gfx_resume()
2756 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); in gfx_v12_0_cp_gfx_resume()
2758 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); in gfx_v12_0_cp_gfx_resume()
2777 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v12_0_cp_compute_enable()
2798 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); in gfx_v12_0_cp_compute_enable()
2864 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); in gfx_v12_0_cp_compute_load_microcode_rs64()
2868 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v12_0_cp_compute_load_microcode_rs64()
2870 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); in gfx_v12_0_cp_compute_load_microcode_rs64()
2873 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); in gfx_v12_0_cp_compute_load_microcode_rs64()
2879 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, in gfx_v12_0_cp_compute_load_microcode_rs64()
2882 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, in gfx_v12_0_cp_compute_load_microcode_rs64()
2886 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, in gfx_v12_0_cp_compute_load_microcode_rs64()
2888 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, in gfx_v12_0_cp_compute_load_microcode_rs64()
2895 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); in gfx_v12_0_cp_compute_load_microcode_rs64()
2897 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); in gfx_v12_0_cp_compute_load_microcode_rs64()
2901 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); in gfx_v12_0_cp_compute_load_microcode_rs64()
2914 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v12_0_cp_compute_load_microcode_rs64()
2916 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); in gfx_v12_0_cp_compute_load_microcode_rs64()
2920 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v12_0_cp_compute_load_microcode_rs64()
2943 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); in gfx_v12_0_kiq_setting()
2946 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); in gfx_v12_0_kiq_setting()
2952 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, in gfx_v12_0_cp_set_doorbell_range()
2954 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, in gfx_v12_0_cp_set_doorbell_range()
2958 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, in gfx_v12_0_cp_set_doorbell_range()
2960 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, in gfx_v12_0_cp_set_doorbell_range()
3248 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); in gfx_v12_0_kiq_init_register()
3251 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v12_0_kiq_init_register()
3254 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, in gfx_v12_0_kiq_init_register()
3256 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, in gfx_v12_0_kiq_init_register()
3260 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, in gfx_v12_0_kiq_init_register()
3264 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v12_0_kiq_init_register()
3268 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { in gfx_v12_0_kiq_init_register()
3269 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v12_0_kiq_init_register()
3271 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in gfx_v12_0_kiq_init_register()
3275 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, in gfx_v12_0_kiq_init_register()
3277 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, in gfx_v12_0_kiq_init_register()
3279 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, in gfx_v12_0_kiq_init_register()
3281 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, in gfx_v12_0_kiq_init_register()
3286 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, in gfx_v12_0_kiq_init_register()
3288 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, in gfx_v12_0_kiq_init_register()
3292 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, in gfx_v12_0_kiq_init_register()
3296 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, in gfx_v12_0_kiq_init_register()
3298 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, in gfx_v12_0_kiq_init_register()
3302 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, in gfx_v12_0_kiq_init_register()
3306 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, in gfx_v12_0_kiq_init_register()
3308 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, in gfx_v12_0_kiq_init_register()
3312 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, in gfx_v12_0_kiq_init_register()
3314 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, in gfx_v12_0_kiq_init_register()
3319 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, in gfx_v12_0_kiq_init_register()
3321 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, in gfx_v12_0_kiq_init_register()
3325 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v12_0_kiq_init_register()
3329 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, in gfx_v12_0_kiq_init_register()
3331 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, in gfx_v12_0_kiq_init_register()
3335 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); in gfx_v12_0_kiq_init_register()
3337 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, in gfx_v12_0_kiq_init_register()
3341 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, in gfx_v12_0_kiq_init_register()
3345 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); in gfx_v12_0_kiq_init_register()
3538 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); in get_gb_addr_config()
3574 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); in gfx_v12_0_disable_gpa_mode()
3576 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); in gfx_v12_0_disable_gpa_mode()
3578 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); in gfx_v12_0_disable_gpa_mode()
3580 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); in gfx_v12_0_disable_gpa_mode()
3765 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); in gfx_v12_0_hw_fini()
3767 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); in gfx_v12_0_hw_fini()
3795 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), in gfx_v12_0_is_idle()
3810 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & in gfx_v12_0_wait_for_idle()
3906 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); in gfx_v12_0_is_rlc_enabled()
3919 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); in gfx_v12_0_set_safe_mode()
3923 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), in gfx_v12_0_set_safe_mode()
3933 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); in gfx_v12_0_unset_safe_mode()
3944 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v12_0_update_perf_clk()
3952 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v12_0_update_perf_clk()
3961 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); in gfx_v12_0_update_spm_vmid()
3971 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); in gfx_v12_0_update_spm_vmid()
3973 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); in gfx_v12_0_update_spm_vmid()
3979 uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); in gfx_v12_0_update_spm_vmid()
4044 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v12_0_update_coarse_grain_clock_gating()
4057 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v12_0_update_coarse_grain_clock_gating()
4060 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v12_0_update_coarse_grain_clock_gating()
4075 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); in gfx_v12_0_update_coarse_grain_clock_gating()
4078 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); in gfx_v12_0_update_coarse_grain_clock_gating()
4093 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); in gfx_v12_0_update_coarse_grain_clock_gating()
4096 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); in gfx_v12_0_update_coarse_grain_clock_gating()
4103 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); in gfx_v12_0_update_coarse_grain_clock_gating()
4105 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); in gfx_v12_0_update_coarse_grain_clock_gating()
4110 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); in gfx_v12_0_update_coarse_grain_clock_gating()
4112 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); in gfx_v12_0_update_coarse_grain_clock_gating()
4114 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); in gfx_v12_0_update_coarse_grain_clock_gating()
4118 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); in gfx_v12_0_update_coarse_grain_clock_gating()
4120 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); in gfx_v12_0_update_coarse_grain_clock_gating()
4124 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v12_0_update_coarse_grain_clock_gating()
4133 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); in gfx_v12_0_update_coarse_grain_clock_gating()
4136 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); in gfx_v12_0_update_coarse_grain_clock_gating()
4144 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); in gfx_v12_0_update_coarse_grain_clock_gating()
4159 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v12_0_update_medium_grain_clock_gating()
4166 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v12_0_update_medium_grain_clock_gating()
4170 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v12_0_update_medium_grain_clock_gating()
4177 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v12_0_update_medium_grain_clock_gating()
4190 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v12_0_update_repeater_fgcg()
4200 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v12_0_update_repeater_fgcg()
4211 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v12_0_update_sram_fgcg()
4219 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v12_0_update_sram_fgcg()
4277 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v12_0_get_clockgating_state()
4294 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v12_0_get_clockgating_state()
4303 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); in gfx_v12_0_get_clockgating_state()
4327 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); in gfx_v12_0_ring_get_wptr_gfx()
4328 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; in gfx_v12_0_ring_get_wptr_gfx()
4344 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, in gfx_v12_0_ring_set_wptr_gfx()
4346 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, in gfx_v12_0_ring_set_wptr_gfx()
4543 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); in gfx_v12_0_ring_emit_fence_kiq()
4713 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); in gfx_v12_0_set_gfx_eop_interrupt_state()
4726 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v12_0_set_gfx_eop_interrupt_state()
4731 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v12_0_set_gfx_eop_interrupt_state()
4734 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v12_0_set_gfx_eop_interrupt_state()
4739 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v12_0_set_gfx_eop_interrupt_state()
4761 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); in gfx_v12_0_set_compute_eop_interrupt_state()
4764 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); in gfx_v12_0_set_compute_eop_interrupt_state()
4777 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v12_0_set_compute_eop_interrupt_state()
4782 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v12_0_set_compute_eop_interrupt_state()
4785 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v12_0_set_compute_eop_interrupt_state()
4790 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v12_0_set_compute_eop_interrupt_state()
4896 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v12_0_set_priv_reg_fault_state()
4900 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v12_0_set_priv_reg_fault_state()
4910 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v12_0_set_priv_reg_fault_state()
4914 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v12_0_set_priv_reg_fault_state()
4942 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v12_0_set_bad_op_fault_state()
4946 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v12_0_set_bad_op_fault_state()
4956 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v12_0_set_bad_op_fault_state()
4960 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v12_0_set_bad_op_fault_state()
4987 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v12_0_set_priv_inst_fault_state()
4991 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v12_0_set_priv_inst_fault_state()
5287 WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe); in gfx_v12_reset_gfx_pipe()
5288 WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe); in gfx_v12_reset_gfx_pipe()
5290 r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) - in gfx_v12_reset_gfx_pipe()
5350 reset_pipe = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v12_0_reset_compute_pipe()
5382 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_pipe); in gfx_v12_0_reset_compute_pipe()
5383 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_pipe); in gfx_v12_0_reset_compute_pipe()
5384 r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) - in gfx_v12_0_reset_compute_pipe()
5403 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_pipe); in gfx_v12_0_reset_compute_pipe()
5404 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_pipe); in gfx_v12_0_reset_compute_pipe()
5688 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); in gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh()
5694 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); in gfx_v12_0_get_wgp_active_bitmap_per_sh()
5695 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); in gfx_v12_0_get_wgp_active_bitmap_per_sh()