Lines Matching refs:mec
772 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); in gfx_v12_0_mec_fini()
773 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); in gfx_v12_0_mec_fini()
774 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); in gfx_v12_0_mec_fini()
799 &adev->gfx.mec.hpd_eop_obj, in gfx_v12_0_mec_init()
800 &adev->gfx.mec.hpd_eop_gpu_addr, in gfx_v12_0_mec_init()
810 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); in gfx_v12_0_mec_init()
811 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v12_0_mec_init()
995 int mec, int pipe, int queue) in gfx_v12_0_compute_ring_init() argument
1005 ring->me = mec + 1; in gfx_v12_0_compute_ring_init()
1012 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr in gfx_v12_0_compute_ring_init()
1018 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) in gfx_v12_0_compute_ring_init()
1367 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v12_0_alloc_ip_dump()
1368 adev->gfx.mec.num_queue_per_pipe; in gfx_v12_0_alloc_ip_dump()
1408 adev->gfx.mec.num_mec = 1; in gfx_v12_0_sw_init()
1409 adev->gfx.mec.num_pipe_per_mec = 2; in gfx_v12_0_sw_init()
1410 adev->gfx.mec.num_queue_per_pipe = 4; in gfx_v12_0_sw_init()
1416 adev->gfx.mec.num_mec = 1; in gfx_v12_0_sw_init()
1417 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v12_0_sw_init()
1418 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v12_0_sw_init()
1454 num_compute_rings = (adev->gfx.mec.num_pipe_per_mec * in gfx_v12_0_sw_init()
1455 adev->gfx.mec.num_queue_per_pipe) / 2; in gfx_v12_0_sw_init()
1525 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v12_0_sw_init()
1526 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v12_0_sw_init()
1527 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v12_0_sw_init()
2281 for (pipe_id = 0; pipe_id < adev->gfx.mec.num_pipe_per_mec; pipe_id++) { in gfx_v12_0_set_mec_ucode_start_addr()
2832 &adev->gfx.mec.mec_fw_obj, in gfx_v12_0_cp_compute_load_microcode_rs64()
2833 &adev->gfx.mec.mec_fw_gpu_addr, in gfx_v12_0_cp_compute_load_microcode_rs64()
2843 adev->gfx.mec.num_pipe_per_mec, in gfx_v12_0_cp_compute_load_microcode_rs64()
2845 &adev->gfx.mec.mec_fw_data_obj, in gfx_v12_0_cp_compute_load_microcode_rs64()
2846 &adev->gfx.mec.mec_fw_data_gpu_addr, in gfx_v12_0_cp_compute_load_microcode_rs64()
2855 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { in gfx_v12_0_cp_compute_load_microcode_rs64()
2859 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); in gfx_v12_0_cp_compute_load_microcode_rs64()
2860 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); in gfx_v12_0_cp_compute_load_microcode_rs64()
2861 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); in gfx_v12_0_cp_compute_load_microcode_rs64()
2862 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); in gfx_v12_0_cp_compute_load_microcode_rs64()
2876 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { in gfx_v12_0_cp_compute_load_microcode_rs64()
2880 lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + in gfx_v12_0_cp_compute_load_microcode_rs64()
2883 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + in gfx_v12_0_cp_compute_load_microcode_rs64()
2887 lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); in gfx_v12_0_cp_compute_load_microcode_rs64()
2889 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); in gfx_v12_0_cp_compute_load_microcode_rs64()
3360 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v12_0_kiq_init_queue()
3361 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v12_0_kiq_init_queue()
3383 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v12_0_kiq_init_queue()
3384 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v12_0_kiq_init_queue()
3404 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v12_0_kcq_init_queue()
3405 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v12_0_kcq_init_queue()
3408 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v12_0_kcq_init_queue()
3409 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v12_0_kcq_init_queue()
3718 for (m = 0; m < adev->gfx.mec.num_mec; ++m) { in gfx_v12_0_set_userq_eop_interrupts()
3719 for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) { in gfx_v12_0_set_userq_eop_interrupts()
3721 + (m * adev->gfx.mec.num_pipe_per_mec) in gfx_v12_0_set_userq_eop_interrupts()
4904 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v12_0_set_priv_reg_fault_state()
4905 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v12_0_set_priv_reg_fault_state()
4950 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v12_0_set_bad_op_fault_state()
4951 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v12_0_set_bad_op_fault_state()
5132 adev->gfx.mec.num_mec, in gfx_v12_ip_print()
5133 adev->gfx.mec.num_pipe_per_mec, in gfx_v12_ip_print()
5134 adev->gfx.mec.num_queue_per_pipe); in gfx_v12_ip_print()
5136 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v12_ip_print()
5137 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v12_ip_print()
5138 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v12_ip_print()
5197 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v12_ip_dump()
5198 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v12_ip_dump()
5199 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v12_ip_dump()