Lines Matching refs:mqd
2967 struct v12_gfx_mqd *mqd = m; in gfx_v12_0_gfx_mqd_init() local
2973 mqd->cp_gfx_hqd_wptr = 0; in gfx_v12_0_gfx_mqd_init()
2974 mqd->cp_gfx_hqd_wptr_hi = 0; in gfx_v12_0_gfx_mqd_init()
2977 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; in gfx_v12_0_gfx_mqd_init()
2978 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); in gfx_v12_0_gfx_mqd_init()
2985 mqd->cp_gfx_mqd_control = tmp; in gfx_v12_0_gfx_mqd_init()
2990 mqd->cp_gfx_hqd_vmid = 0; in gfx_v12_0_gfx_mqd_init()
2996 mqd->cp_gfx_hqd_queue_priority = tmp; in gfx_v12_0_gfx_mqd_init()
3001 mqd->cp_gfx_hqd_quantum = tmp; in gfx_v12_0_gfx_mqd_init()
3005 mqd->cp_gfx_hqd_base = hqd_gpu_addr; in gfx_v12_0_gfx_mqd_init()
3006 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); in gfx_v12_0_gfx_mqd_init()
3010 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; in gfx_v12_0_gfx_mqd_init()
3011 mqd->cp_gfx_hqd_rptr_addr_hi = in gfx_v12_0_gfx_mqd_init()
3016 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v12_0_gfx_mqd_init()
3017 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v12_0_gfx_mqd_init()
3029 mqd->cp_gfx_hqd_cntl = tmp; in gfx_v12_0_gfx_mqd_init()
3041 mqd->cp_rb_doorbell_control = tmp; in gfx_v12_0_gfx_mqd_init()
3044 mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT; in gfx_v12_0_gfx_mqd_init()
3047 mqd->cp_gfx_hqd_active = 1; in gfx_v12_0_gfx_mqd_init()
3050 mqd->shadow_base_lo = lower_32_bits(prop->shadow_addr); in gfx_v12_0_gfx_mqd_init()
3051 mqd->shadow_base_hi = upper_32_bits(prop->shadow_addr); in gfx_v12_0_gfx_mqd_init()
3052 mqd->fw_work_area_base_lo = lower_32_bits(prop->csa_addr); in gfx_v12_0_gfx_mqd_init()
3053 mqd->fw_work_area_base_hi = upper_32_bits(prop->csa_addr); in gfx_v12_0_gfx_mqd_init()
3054 mqd->fence_address_lo = lower_32_bits(prop->fence_address); in gfx_v12_0_gfx_mqd_init()
3055 mqd->fence_address_hi = upper_32_bits(prop->fence_address); in gfx_v12_0_gfx_mqd_init()
3063 struct v12_gfx_mqd *mqd = ring->mqd_ptr; in gfx_v12_0_kgq_init_queue() local
3067 memset((void *)mqd, 0, sizeof(*mqd)); in gfx_v12_0_kgq_init_queue()
3074 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v12_0_kgq_init_queue()
3078 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v12_0_kgq_init_queue()
3108 struct v12_compute_mqd *mqd = m; in gfx_v12_0_compute_mqd_init() local
3112 mqd->header = 0xC0310800; in gfx_v12_0_compute_mqd_init()
3113 mqd->compute_pipelinestat_enable = 0x00000001; in gfx_v12_0_compute_mqd_init()
3114 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; in gfx_v12_0_compute_mqd_init()
3115 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; in gfx_v12_0_compute_mqd_init()
3116 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; in gfx_v12_0_compute_mqd_init()
3117 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; in gfx_v12_0_compute_mqd_init()
3118 mqd->compute_misc_reserved = 0x00000007; in gfx_v12_0_compute_mqd_init()
3121 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; in gfx_v12_0_compute_mqd_init()
3122 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); in gfx_v12_0_compute_mqd_init()
3129 mqd->cp_hqd_eop_control = tmp; in gfx_v12_0_compute_mqd_init()
3148 mqd->cp_hqd_pq_doorbell_control = tmp; in gfx_v12_0_compute_mqd_init()
3151 mqd->cp_hqd_dequeue_request = 0; in gfx_v12_0_compute_mqd_init()
3152 mqd->cp_hqd_pq_rptr = 0; in gfx_v12_0_compute_mqd_init()
3153 mqd->cp_hqd_pq_wptr_lo = 0; in gfx_v12_0_compute_mqd_init()
3154 mqd->cp_hqd_pq_wptr_hi = 0; in gfx_v12_0_compute_mqd_init()
3157 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; in gfx_v12_0_compute_mqd_init()
3158 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); in gfx_v12_0_compute_mqd_init()
3163 mqd->cp_mqd_control = tmp; in gfx_v12_0_compute_mqd_init()
3167 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; in gfx_v12_0_compute_mqd_init()
3168 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in gfx_v12_0_compute_mqd_init()
3182 mqd->cp_hqd_pq_control = tmp; in gfx_v12_0_compute_mqd_init()
3186 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v12_0_compute_mqd_init()
3187 mqd->cp_hqd_pq_rptr_report_addr_hi = in gfx_v12_0_compute_mqd_init()
3192 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v12_0_compute_mqd_init()
3193 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v12_0_compute_mqd_init()
3210 mqd->cp_hqd_pq_doorbell_control = tmp; in gfx_v12_0_compute_mqd_init()
3213 mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT; in gfx_v12_0_compute_mqd_init()
3216 mqd->cp_hqd_vmid = 0; in gfx_v12_0_compute_mqd_init()
3220 mqd->cp_hqd_persistent_state = tmp; in gfx_v12_0_compute_mqd_init()
3225 mqd->cp_hqd_ib_control = tmp; in gfx_v12_0_compute_mqd_init()
3228 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; in gfx_v12_0_compute_mqd_init()
3229 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; in gfx_v12_0_compute_mqd_init()
3231 mqd->cp_hqd_active = prop->hqd_active; in gfx_v12_0_compute_mqd_init()
3234 mqd->fence_address_lo = lower_32_bits(prop->fence_address); in gfx_v12_0_compute_mqd_init()
3235 mqd->fence_address_hi = upper_32_bits(prop->fence_address); in gfx_v12_0_compute_mqd_init()
3243 struct v12_compute_mqd *mqd = ring->mqd_ptr; in gfx_v12_0_kiq_init_register() local
3255 mqd->cp_hqd_eop_base_addr_lo); in gfx_v12_0_kiq_init_register()
3257 mqd->cp_hqd_eop_base_addr_hi); in gfx_v12_0_kiq_init_register()
3261 mqd->cp_hqd_eop_control); in gfx_v12_0_kiq_init_register()
3265 mqd->cp_hqd_pq_doorbell_control); in gfx_v12_0_kiq_init_register()
3276 mqd->cp_hqd_dequeue_request); in gfx_v12_0_kiq_init_register()
3278 mqd->cp_hqd_pq_rptr); in gfx_v12_0_kiq_init_register()
3280 mqd->cp_hqd_pq_wptr_lo); in gfx_v12_0_kiq_init_register()
3282 mqd->cp_hqd_pq_wptr_hi); in gfx_v12_0_kiq_init_register()
3287 mqd->cp_mqd_base_addr_lo); in gfx_v12_0_kiq_init_register()
3289 mqd->cp_mqd_base_addr_hi); in gfx_v12_0_kiq_init_register()
3293 mqd->cp_mqd_control); in gfx_v12_0_kiq_init_register()
3297 mqd->cp_hqd_pq_base_lo); in gfx_v12_0_kiq_init_register()
3299 mqd->cp_hqd_pq_base_hi); in gfx_v12_0_kiq_init_register()
3303 mqd->cp_hqd_pq_control); in gfx_v12_0_kiq_init_register()
3307 mqd->cp_hqd_pq_rptr_report_addr_lo); in gfx_v12_0_kiq_init_register()
3309 mqd->cp_hqd_pq_rptr_report_addr_hi); in gfx_v12_0_kiq_init_register()
3313 mqd->cp_hqd_pq_wptr_poll_addr_lo); in gfx_v12_0_kiq_init_register()
3315 mqd->cp_hqd_pq_wptr_poll_addr_hi); in gfx_v12_0_kiq_init_register()
3326 mqd->cp_hqd_pq_doorbell_control); in gfx_v12_0_kiq_init_register()
3330 mqd->cp_hqd_pq_wptr_lo); in gfx_v12_0_kiq_init_register()
3332 mqd->cp_hqd_pq_wptr_hi); in gfx_v12_0_kiq_init_register()
3335 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); in gfx_v12_0_kiq_init_register()
3338 mqd->cp_hqd_persistent_state); in gfx_v12_0_kiq_init_register()
3342 mqd->cp_hqd_active); in gfx_v12_0_kiq_init_register()
3353 struct v12_compute_mqd *mqd = ring->mqd_ptr; in gfx_v12_0_kiq_init_queue() local
3361 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v12_0_kiq_init_queue()
3373 memset((void *)mqd, 0, sizeof(*mqd)); in gfx_v12_0_kiq_init_queue()
3384 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v12_0_kiq_init_queue()
3393 struct v12_compute_mqd *mqd = ring->mqd_ptr; in gfx_v12_0_kcq_init_queue() local
3397 memset((void *)mqd, 0, sizeof(*mqd)); in gfx_v12_0_kcq_init_queue()
3405 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v12_0_kcq_init_queue()
3409 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v12_0_kcq_init_queue()