Lines Matching refs:NUM_BANKS
101 #define NUM_BANKS(x) ((x) << 20) macro
429 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
437 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
445 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
452 NUM_BANKS(ADDR_SURF_8_BANK) | in gfx_v6_0_tiling_mode_table_init()
464 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
472 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
480 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
492 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
500 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
508 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
519 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
527 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
535 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
542 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
553 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
561 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
570 NUM_BANKS(ADDR_SURF_8_BANK); in gfx_v6_0_tiling_mode_table_init()
578 NUM_BANKS(ADDR_SURF_8_BANK); in gfx_v6_0_tiling_mode_table_init()
586 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
594 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
602 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
610 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
618 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
626 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
634 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
642 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
650 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
658 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
666 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
674 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
682 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
690 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
698 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
706 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
714 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
722 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
730 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
738 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
746 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
754 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
762 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
770 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
778 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
786 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
799 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
807 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
813 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
821 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
829 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
837 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
845 NUM_BANKS(ADDR_SURF_8_BANK) | in gfx_v6_0_tiling_mode_table_init()
859 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
867 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
875 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
882 NUM_BANKS(ADDR_SURF_8_BANK) | in gfx_v6_0_tiling_mode_table_init()
894 NUM_BANKS(ADDR_SURF_8_BANK); in gfx_v6_0_tiling_mode_table_init()
902 NUM_BANKS(ADDR_SURF_8_BANK); in gfx_v6_0_tiling_mode_table_init()
910 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
922 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
930 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
938 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
949 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
957 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
965 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
972 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
983 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
991 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
1000 NUM_BANKS(ADDR_SURF_8_BANK); in gfx_v6_0_tiling_mode_table_init()
1008 NUM_BANKS(ADDR_SURF_8_BANK); in gfx_v6_0_tiling_mode_table_init()
1016 NUM_BANKS(ADDR_SURF_8_BANK); in gfx_v6_0_tiling_mode_table_init()
1024 NUM_BANKS(ADDR_SURF_8_BANK); in gfx_v6_0_tiling_mode_table_init()
1032 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
1040 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
1048 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
1056 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
1064 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
1072 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
1083 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
1091 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
1099 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
1106 NUM_BANKS(ADDR_SURF_4_BANK) | in gfx_v6_0_tiling_mode_table_init()
1118 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
1126 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
1134 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
1146 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
1154 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
1162 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
1173 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
1181 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
1189 NUM_BANKS(ADDR_SURF_16_BANK); in gfx_v6_0_tiling_mode_table_init()
1196 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
1207 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
1215 NUM_BANKS(ADDR_SURF_16_BANK) | in gfx_v6_0_tiling_mode_table_init()
1224 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
1232 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
1240 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
1248 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
1256 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
1264 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
1272 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
1280 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
1288 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
1296 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()