Lines Matching refs:PACKET3
936 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx_v9_0_kiq_set_resources()
958 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx_v9_0_kiq_map_queues()
988 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); in gfx_v9_0_kiq_unmap_queues()
1016 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); in gfx_v9_0_kiq_query_status()
1035 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); in gfx_v9_0_kiq_invalidate_tlbs()
1163 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v9_0_write_data_to_reg()
1177 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v9_0_wait_reg_mem()
1207 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v9_0_ring_test_ring()
1247 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v9_0_ring_test_ib()
3343 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v9_0_cp_gfx_start()
3346 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); in gfx_v9_0_cp_gfx_start()
3354 PACKET3(PACKET3_SET_CONTEXT_REG, in gfx_v9_0_cp_gfx_start()
3364 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v9_0_cp_gfx_start()
3367 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v9_0_cp_gfx_start()
3370 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v9_0_cp_gfx_start()
3375 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1)); in gfx_v9_0_cp_gfx_start()
4212 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); in gfx_v9_0_kiq_read_clock()
4592 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); in gfx_v9_0_do_edc_gds_workarounds()
4690 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); in gfx_v9_0_do_edc_gpr_workarounds()
4697 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); in gfx_v9_0_do_edc_gpr_workarounds()
4704 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); in gfx_v9_0_do_edc_gpr_workarounds()
4712 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); in gfx_v9_0_do_edc_gpr_workarounds()
4718 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); in gfx_v9_0_do_edc_gpr_workarounds()
4725 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); in gfx_v9_0_do_edc_gpr_workarounds()
4732 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); in gfx_v9_0_do_edc_gpr_workarounds()
4740 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); in gfx_v9_0_do_edc_gpr_workarounds()
4746 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); in gfx_v9_0_do_edc_gpr_workarounds()
4753 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); in gfx_v9_0_do_edc_gpr_workarounds()
4760 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); in gfx_v9_0_do_edc_gpr_workarounds()
4768 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); in gfx_v9_0_do_edc_gpr_workarounds()
5416 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in gfx_v9_0_ring_emit_ib_gfx()
5418 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v9_0_ring_emit_ib_gfx()
5527 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v9_0_ring_emit_ib_compute()
5532 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); in gfx_v9_0_ring_emit_ib_compute()
5553 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); in gfx_v9_0_ring_emit_fence()
5603 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in gfx_v9_0_ring_emit_vm_flush()
5647 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v9_0_ring_emit_fence_kiq()
5656 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v9_0_ring_emit_fence_kiq()
5667 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v9_ring_emit_sb()
5685 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); in gfx_v9_0_ring_emit_ce_meta()
5783 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); in gfx_v9_0_ring_emit_de_meta()
5805 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); in gfx_v9_0_ring_emit_frame_cntl()
5837 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); in gfx_v9_ring_emit_cntxcntl()
5846 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); in gfx_v9_0_ring_emit_init_cond_exec()
5862 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); in gfx_v9_0_ring_emit_rreg()
5890 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v9_0_ring_emit_wreg()
7093 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); in gfx_v9_0_emit_mem_sync()
7170 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); in gfx_v9_ring_insert_nop()
7346 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); in gfx_v9_0_ring_emit_cleaner_shader()
7348 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER_9_0, 0)); in gfx_v9_0_ring_emit_cleaner_shader()
7408 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
7464 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
7524 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
7567 .nop = PACKET3(PACKET3_NOP, 0x3FFF),