Lines Matching refs:mec
1865 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); in gfx_v9_0_mec_fini()
1866 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); in gfx_v9_0_mec_fini()
1889 &adev->gfx.mec.hpd_eop_obj, in gfx_v9_0_mec_init()
1890 &adev->gfx.mec.hpd_eop_gpu_addr, in gfx_v9_0_mec_init()
1900 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); in gfx_v9_0_mec_init()
1901 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v9_0_mec_init()
1913 &adev->gfx.mec.mec_fw_obj, in gfx_v9_0_mec_init()
1914 &adev->gfx.mec.mec_fw_gpu_addr, in gfx_v9_0_mec_init()
1924 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); in gfx_v9_0_mec_init()
1925 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); in gfx_v9_0_mec_init()
2154 int mec, int pipe, int queue) in gfx_v9_0_compute_ring_init() argument
2163 ring->me = mec + 1; in gfx_v9_0_compute_ring_init()
2170 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr in gfx_v9_0_compute_ring_init()
2176 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) in gfx_v9_0_compute_ring_init()
2201 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v9_0_alloc_ip_dump()
2202 adev->gfx.mec.num_queue_per_pipe; in gfx_v9_0_alloc_ip_dump()
2230 adev->gfx.mec.num_mec = 2; in gfx_v9_0_sw_init()
2233 adev->gfx.mec.num_mec = 1; in gfx_v9_0_sw_init()
2274 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v9_0_sw_init()
2275 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v9_0_sw_init()
2390 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v9_0_sw_init()
2391 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v9_0_sw_init()
2392 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v9_0_sw_init()
3499 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); in gfx_v9_0_cp_compute_load_microcode()
3501 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); in gfx_v9_0_cp_compute_load_microcode()
3886 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; in gfx_v9_0_kcq_init_queue()
3899 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v9_0_kcq_init_queue()
3900 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); in gfx_v9_0_kcq_init_queue()
3903 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v9_0_kcq_init_queue()
3904 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); in gfx_v9_0_kcq_init_queue()
6041 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v9_0_set_priv_reg_fault_state()
6042 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v9_0_set_priv_reg_fault_state()
6077 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v9_0_set_bad_op_fault_state()
6078 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v9_0_set_bad_op_fault_state()
7154 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { in gfx_v9_0_emit_wave_limit()
7269 adev->gfx.mec.num_mec, in gfx_v9_ip_print()
7270 adev->gfx.mec.num_pipe_per_mec, in gfx_v9_ip_print()
7271 adev->gfx.mec.num_queue_per_pipe); in gfx_v9_ip_print()
7273 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v9_ip_print()
7274 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v9_ip_print()
7275 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v9_ip_print()
7315 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v9_ip_dump()
7316 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v9_ip_dump()
7317 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v9_ip_dump()