Lines Matching refs:GC
41 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, 1 },
42 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, 1 },
44 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1 },
45 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, 1 },
46 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, 1 },
48 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, 1 },
49 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, 1 },
51 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1 },
52 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT), 0, 1, 1 },
53 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_DED), 0, 1, 1 },
54 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1, 1 },
55 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, 1 },
57 { SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 0, 4, 1 },
59 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 0, 8, 16 },
60 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_DED_CNT), 0, 8, 16 },
61 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_INFO), 0, 8, 16 },
62 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_SEC_CNT), 0, 8, 16 },
64 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 0, 4, 6 },
65 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 0, 4, 6 },
66 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6 },
67 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3), 0, 4, 6 },
69 { SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 0, 4, 16 },
71 { SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2 },
73 { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 1, 16 },
74 { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16 },
76 { SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 0, 1, 72 },
78 { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 0, 4, 16 },
79 { SOC15_REG_ENTRY(GC, 0, mmTCP_ATC_EDC_GATCL1_CNT), 0, 4, 16 },
80 { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT), 0, 4, 16 },
82 { SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 0, 4, 16 },
84 { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 1, 32 },
85 { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 1, 32 },
86 { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 1, 32 },
88 { SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT), 0, 1, 1 },
89 { SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2), 0, 1, 1 },
116 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data); in gfx_v9_4_select_se_sh()
121 { "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT),
124 { "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT),
127 { "CPC_DC_STATE_RAM_ME1", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT),
131 SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT),
135 SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT),
139 SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT),
143 SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT),
148 { "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT),
151 { "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT),
154 { "CPF_TCIU_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT),
159 { "GDS_GRBM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT),
162 { "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT),
165 { "GDS_PHY_CMD_RAM_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
168 { "GDS_PHY_DATA_RAM_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
171 { "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
175 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
179 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
183 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
187 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
192 { "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
195 { "SPI_GDS_EXPREQ", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
198 { "SPI_WB_GRANT_30", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
201 { "SPI_WB_GRANT_61", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
204 { "SPI_LIFE_CNT", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
209 { "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
212 { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
215 { "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
218 { "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
221 { "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
224 { "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
227 { "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
232 { "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
235 { "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
238 { "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
241 { "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
244 { "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
247 { "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
250 { "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
253 { "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
257 SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
263 SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
267 { "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
270 { "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
274 SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
278 SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
282 { "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
285 { "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
289 SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
295 SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
299 { "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
302 { "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
306 SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
310 SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
314 { "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
319 { "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
322 { "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
325 { "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
328 { "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
331 { "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
336 { "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT),
339 { "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT),
344 { "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
347 { "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
350 { "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
353 { "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
356 { "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
359 { "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
362 { "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
365 { "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
368 { "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
371 { "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
374 { "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
377 { "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
380 { "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
383 { "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
386 { "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
391 { "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT),
396 { "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
399 { "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
402 { "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
405 { "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
408 { "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
410 { "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
413 { "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
418 { "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
421 { "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
424 { "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
429 { "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
432 { "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
435 { "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
438 { "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
441 { "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
444 { "EA_GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
447 { "EA_GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
450 { "EA_GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
453 { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
455 { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
457 { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
459 { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
461 { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
463 { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
465 { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
467 { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
469 { "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
471 { "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
473 { "EA_GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
475 { "EA_GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
477 { "EA_GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
479 { "EA_GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
481 { "EA_MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
484 { "EA_MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
487 { "EA_MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
490 { "EA_MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
493 { "EA_MAM_A0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3),
496 { "EA_MAM_A1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3),
499 { "EA_MAM_A2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3),
502 { "EA_MAM_A3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3),
505 { "EA_MAM_AFMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
507 { "EA_MAM_AFMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
511 { "RLCG_INSTR_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
514 { "RLCG_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
517 { "RLCV_INSTR_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
520 { "RLCV_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
523 { "RLC_TCTAG_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
526 { "RLC_SPM_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
529 { "RLC_SRM_DATA_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
532 { "RLC_SRM_ADDR_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
535 { "RLC_SPM_SE0_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
538 { "RLC_SPM_SE1_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
541 { "RLC_SPM_SE2_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
544 { "RLC_SPM_SE3_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
547 { "RLC_SPM_SE4_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
550 { "RLC_SPM_SE5_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
553 { "RLC_SPM_SE6_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
556 { "RLC_SPM_SE7_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
694 WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, 255); in gfx_v9_4_query_utc_edc_status()
695 WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL, 0); in gfx_v9_4_query_utc_edc_status()
696 WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, 255); in gfx_v9_4_query_utc_edc_status()
697 WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_CNTL, 0); in gfx_v9_4_query_utc_edc_status()
698 WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, 255); in gfx_v9_4_query_utc_edc_status()
699 WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL, 0); in gfx_v9_4_query_utc_edc_status()
701 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, 255); in gfx_v9_4_query_utc_edc_status()
702 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0); in gfx_v9_4_query_utc_edc_status()
703 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, 255); in gfx_v9_4_query_utc_edc_status()
704 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0); in gfx_v9_4_query_utc_edc_status()
707 WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, i); in gfx_v9_4_query_utc_edc_status()
708 data = RREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL); in gfx_v9_4_query_utc_edc_status()
728 WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, i); in gfx_v9_4_query_utc_edc_status()
729 data = RREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_CNTL); in gfx_v9_4_query_utc_edc_status()
751 WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, i); in gfx_v9_4_query_utc_edc_status()
752 data = RREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL); in gfx_v9_4_query_utc_edc_status()
772 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, i); in gfx_v9_4_query_utc_edc_status()
773 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL); in gfx_v9_4_query_utc_edc_status()
795 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, i); in gfx_v9_4_query_utc_edc_status()
796 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_CNTL); in gfx_v9_4_query_utc_edc_status()
817 WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, 255); in gfx_v9_4_query_utc_edc_status()
818 WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, 255); in gfx_v9_4_query_utc_edc_status()
819 WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, 255); in gfx_v9_4_query_utc_edc_status()
820 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, 255); in gfx_v9_4_query_utc_edc_status()
821 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, 255); in gfx_v9_4_query_utc_edc_status()
925 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); in gfx_v9_4_reset_ras_error_count()
928 WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, 255); in gfx_v9_4_reset_ras_error_count()
929 WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL, 0); in gfx_v9_4_reset_ras_error_count()
930 WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, 255); in gfx_v9_4_reset_ras_error_count()
931 WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_CNTL, 0); in gfx_v9_4_reset_ras_error_count()
932 WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, 255); in gfx_v9_4_reset_ras_error_count()
933 WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL, 0); in gfx_v9_4_reset_ras_error_count()
935 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, 255); in gfx_v9_4_reset_ras_error_count()
936 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0); in gfx_v9_4_reset_ras_error_count()
937 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, 255); in gfx_v9_4_reset_ras_error_count()
938 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0); in gfx_v9_4_reset_ras_error_count()
941 WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, i); in gfx_v9_4_reset_ras_error_count()
942 RREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL); in gfx_v9_4_reset_ras_error_count()
946 WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, i); in gfx_v9_4_reset_ras_error_count()
947 RREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_CNTL); in gfx_v9_4_reset_ras_error_count()
951 WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, i); in gfx_v9_4_reset_ras_error_count()
952 RREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL); in gfx_v9_4_reset_ras_error_count()
956 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, i); in gfx_v9_4_reset_ras_error_count()
957 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL); in gfx_v9_4_reset_ras_error_count()
961 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, i); in gfx_v9_4_reset_ras_error_count()
962 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_CNTL); in gfx_v9_4_reset_ras_error_count()
965 WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, 255); in gfx_v9_4_reset_ras_error_count()
966 WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, 255); in gfx_v9_4_reset_ras_error_count()
967 WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, 255); in gfx_v9_4_reset_ras_error_count()
968 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, 255); in gfx_v9_4_reset_ras_error_count()
969 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, 255); in gfx_v9_4_reset_ras_error_count()
973 SOC15_REG_ENTRY(GC, 0, mmGCEA_ERR_STATUS), 0, 1, 32