Lines Matching refs:GC
68 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),
69 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),
70 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1),
71 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2),
72 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1),
73 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1),
74 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT),
75 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT),
76 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT),
77 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS),
78 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR),
79 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS),
80 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS),
81 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS),
82 SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT),
83 SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT),
84 SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS),
85 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS),
86 SOC15_REG_ENTRY_STR(GC, 0, regSQC_DCACHE_UTCL1_STATUS),
87 SOC15_REG_ENTRY_STR(GC, 0, regSQC_ICACHE_UTCL1_STATUS),
88 SOC15_REG_ENTRY_STR(GC, 0, regSQ_UTCL1_STATUS),
89 SOC15_REG_ENTRY_STR(GC, 0, regTCP_UTCL1_STATUS),
90 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS),
91 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_CNTL),
92 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_STATUS),
93 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),
94 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),
95 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR),
96 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC2_INSTR_PNTR),
97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS),
98 SOC15_REG_ENTRY_STR(GC, 0, regRLC_STAT),
99 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_COMMAND),
100 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_MESSAGE),
101 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_1),
102 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_2),
103 SOC15_REG_ENTRY_STR(GC, 0, regSMU_RLC_RESPONSE),
104 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SAFE_MODE),
105 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_SAFE_MODE),
106 SOC15_REG_ENTRY_STR(GC, 0, regRLC_INT_STAT),
107 SOC15_REG_ENTRY_STR(GC, 0, regRLC_GPM_GENERAL_6),
109 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0),
110 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1),
111 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2),
112 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3)
117 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID),
118 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ACTIVE),
119 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE),
120 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY),
121 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY),
122 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM),
123 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE),
124 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI),
125 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR),
126 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR),
127 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI),
128 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),
129 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL),
130 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR),
131 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI),
132 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR),
133 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL),
134 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST),
135 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR),
136 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI),
137 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL),
138 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR),
139 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR),
140 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS),
141 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO),
142 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI),
143 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL),
144 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET),
145 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE),
146 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET),
147 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE),
148 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE),
149 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR),
150 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM),
151 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO),
152 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI),
153 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GFX_STATUS),
154 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
155 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
156 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
157 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
158 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
159 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
160 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
161 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
304 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 0x2); in gfx_v9_4_3_kiq_reset_hw_queue()
305 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_COMPUTE_QUEUE_RESET, 0x1); in gfx_v9_4_3_kiq_reset_hw_queue()
308 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) in gfx_v9_4_3_kiq_reset_hw_queue()
353 dev_inst = GET_INST(GC, i); in gfx_v9_4_3_init_golden_registers()
355 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG, in gfx_v9_4_3_init_golden_registers()
357 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, SPARE, 0x1); in gfx_v9_4_3_init_golden_registers()
425 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); in gfx_v9_4_3_ring_test_ring()
426 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); in gfx_v9_4_3_ring_test_ring()
514 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); in gfx_v9_4_3_get_gpu_clock_counter()
515 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) | in gfx_v9_4_3_get_gpu_clock_counter()
516 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); in gfx_v9_4_3_get_gpu_clock_counter()
713 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); in gfx_v9_4_3_xcc_select_se_sh()
718 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, in wave_read_ind()
723 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); in wave_read_ind()
730 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, in wave_read_regs()
738 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); in wave_read_regs()
784 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); in gfx_v9_4_3_select_me_pipe_q()
792 xcp_ctl = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_HYP_XCP_CTL); in gfx_v9_4_3_get_xccs_per_xcp()
817 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, in gfx_v9_4_3_switch_compute_partition()
1235 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); in gfx_v9_4_3_xcc_init_compute_vmid()
1237 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); in gfx_v9_4_3_xcc_init_compute_vmid()
1238 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); in gfx_v9_4_3_xcc_init_compute_vmid()
1241 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL); in gfx_v9_4_3_xcc_init_compute_vmid()
1243 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); in gfx_v9_4_3_xcc_init_compute_vmid()
1245 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); in gfx_v9_4_3_xcc_init_compute_vmid()
1253 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0); in gfx_v9_4_3_xcc_init_compute_vmid()
1254 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0); in gfx_v9_4_3_xcc_init_compute_vmid()
1255 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0); in gfx_v9_4_3_xcc_init_compute_vmid()
1256 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0); in gfx_v9_4_3_xcc_init_compute_vmid()
1271 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0); in gfx_v9_4_3_xcc_init_gds_vmid()
1272 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0); in gfx_v9_4_3_xcc_init_gds_vmid()
1273 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0); in gfx_v9_4_3_xcc_init_gds_vmid()
1274 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0); in gfx_v9_4_3_xcc_init_gds_vmid()
1289 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_CONFIG1); in gfx_v9_4_3_xcc_init_sq()
1291 WREG32_SOC15(GC, xcc_id, regSQ_CONFIG1, data); in gfx_v9_4_3_xcc_init_sq()
1304 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); in gfx_v9_4_3_xcc_constants_init()
1311 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_constants_init()
1313 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_constants_init()
1320 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_constants_init()
1328 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_constants_init()
1332 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); in gfx_v9_4_3_xcc_constants_init()
1349 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2); in gfx_v9_4_3_constants_init()
1375 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); in gfx_v9_4_3_xcc_enable_save_restore_machine()
1390 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); in gfx_v9_4_3_xcc_disable_gpa_mode()
1392 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); in gfx_v9_4_3_xcc_disable_gpa_mode()
1400 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); in gfx_v9_4_3_is_rlc_enabled()
1414 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); in gfx_v9_4_3_xcc_set_safe_mode()
1418 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) in gfx_v9_4_3_xcc_set_safe_mode()
1430 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); in gfx_v9_4_3_xcc_unset_safe_mode()
1440 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1441 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1442 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1443 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1444 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1445 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1446 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1447 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1473 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0) in gfx_v9_4_3_xcc_wait_for_rlc_serdes()
1497 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) in gfx_v9_4_3_xcc_wait_for_rlc_serdes()
1510 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); in gfx_v9_4_3_xcc_enable_gui_idle_interrupt()
1516 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); in gfx_v9_4_3_xcc_enable_gui_idle_interrupt()
1521 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, in gfx_v9_4_3_xcc_rlc_stop()
1538 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, in gfx_v9_4_3_xcc_rlc_reset()
1541 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, in gfx_v9_4_3_xcc_rlc_reset()
1557 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, in gfx_v9_4_3_xcc_rlc_start()
1580 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6); in gfx_v9_4_3_rlc_start()
1587 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4); in gfx_v9_4_3_rlc_start()
1591 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100); in gfx_v9_4_3_rlc_start()
1614 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, in gfx_v9_4_3_xcc_rlc_load_microcode()
1621 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); in gfx_v9_4_3_xcc_rlc_load_microcode()
1623 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v9_4_3_xcc_rlc_load_microcode()
1643 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); in gfx_v9_4_3_xcc_rlc_resume()
1672 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL); in gfx_v9_4_3_update_spm_vmid()
1683 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); in gfx_v9_4_3_update_spm_vmid()
1685 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); in gfx_v9_4_3_update_spm_vmid()
1690 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)},
1691 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)},
1732 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); in gfx_v9_4_3_xcc_cp_compute_enable()
1734 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, in gfx_v9_4_3_xcc_cp_compute_enable()
1773 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v9_4_3_xcc_cp_compute_load_microcode()
1775 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, in gfx_v9_4_3_xcc_cp_compute_load_microcode()
1777 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, in gfx_v9_4_3_xcc_cp_compute_load_microcode()
1781 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR); in gfx_v9_4_3_xcc_cp_compute_load_microcode()
1783 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA); in gfx_v9_4_3_xcc_cp_compute_load_microcode()
1804 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); in gfx_v9_4_3_xcc_kiq_setting()
1807 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp | 0x80); in gfx_v9_4_3_xcc_kiq_setting()
1850 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL); in gfx_v9_4_3_xcc_mqd_init()
1857 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v9_4_3_xcc_mqd_init()
1890 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); in gfx_v9_4_3_xcc_mqd_init()
1900 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL); in gfx_v9_4_3_xcc_mqd_init()
1927 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR); in gfx_v9_4_3_xcc_mqd_init()
1932 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE); in gfx_v9_4_3_xcc_mqd_init()
1937 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL); in gfx_v9_4_3_xcc_mqd_init()
1943 mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); in gfx_v9_4_3_xcc_mqd_init()
1962 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v9_4_3_xcc_kiq_init_register()
1964 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, in gfx_v9_4_3_xcc_kiq_init_register()
1966 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, in gfx_v9_4_3_xcc_kiq_init_register()
1970 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, in gfx_v9_4_3_xcc_kiq_init_register()
1974 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v9_4_3_xcc_kiq_init_register()
1978 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { in gfx_v9_4_3_xcc_kiq_init_register()
1979 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v9_4_3_xcc_kiq_init_register()
1981 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) in gfx_v9_4_3_xcc_kiq_init_register()
1985 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, in gfx_v9_4_3_xcc_kiq_init_register()
1987 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, in gfx_v9_4_3_xcc_kiq_init_register()
1989 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, in gfx_v9_4_3_xcc_kiq_init_register()
1991 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, in gfx_v9_4_3_xcc_kiq_init_register()
1996 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, in gfx_v9_4_3_xcc_kiq_init_register()
1998 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, in gfx_v9_4_3_xcc_kiq_init_register()
2002 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, in gfx_v9_4_3_xcc_kiq_init_register()
2006 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, in gfx_v9_4_3_xcc_kiq_init_register()
2008 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, in gfx_v9_4_3_xcc_kiq_init_register()
2012 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, in gfx_v9_4_3_xcc_kiq_init_register()
2016 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, in gfx_v9_4_3_xcc_kiq_init_register()
2018 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, in gfx_v9_4_3_xcc_kiq_init_register()
2022 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, in gfx_v9_4_3_xcc_kiq_init_register()
2024 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, in gfx_v9_4_3_xcc_kiq_init_register()
2030 GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_kiq_init_register()
2036 GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_kiq_init_register()
2043 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v9_4_3_xcc_kiq_init_register()
2047 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, in gfx_v9_4_3_xcc_kiq_init_register()
2049 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, in gfx_v9_4_3_xcc_kiq_init_register()
2053 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); in gfx_v9_4_3_xcc_kiq_init_register()
2055 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, in gfx_v9_4_3_xcc_kiq_init_register()
2059 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, in gfx_v9_4_3_xcc_kiq_init_register()
2063 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); in gfx_v9_4_3_xcc_kiq_init_register()
2075 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { in gfx_v9_4_3_xcc_q_fini_register()
2077 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v9_4_3_xcc_q_fini_register()
2080 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) in gfx_v9_4_3_xcc_q_fini_register()
2089 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); in gfx_v9_4_3_xcc_q_fini_register()
2092 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, in gfx_v9_4_3_xcc_q_fini_register()
2096 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0); in gfx_v9_4_3_xcc_q_fini_register()
2097 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0); in gfx_v9_4_3_xcc_q_fini_register()
2098 …WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEF… in gfx_v9_4_3_xcc_q_fini_register()
2099 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); in gfx_v9_4_3_xcc_q_fini_register()
2100 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); in gfx_v9_4_3_xcc_q_fini_register()
2101 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); in gfx_v9_4_3_xcc_q_fini_register()
2102 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); in gfx_v9_4_3_xcc_q_fini_register()
2103 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); in gfx_v9_4_3_xcc_q_fini_register()
2131 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); in gfx_v9_4_3_xcc_kiq_init_queue()
2133 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); in gfx_v9_4_3_xcc_kiq_init_queue()
2142 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); in gfx_v9_4_3_xcc_kiq_init_queue()
2145 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); in gfx_v9_4_3_xcc_kiq_init_queue()
2173 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); in gfx_v9_4_3_xcc_kcq_init_queue()
2175 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); in gfx_v9_4_3_xcc_kcq_init_queue()
2204 ring->queue, 0, GET_INST(GC, xcc_id)); in gfx_v9_4_3_xcc_kcq_fini_register()
2206 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); in gfx_v9_4_3_xcc_kcq_fini_register()
2324 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v9_4_3_xcc_fini()
2336 GET_INST(GC, xcc_id)); in gfx_v9_4_3_xcc_fini()
2339 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); in gfx_v9_4_3_xcc_fini()
2405 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), in gfx_v9_4_3_is_idle()
2432 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS); in gfx_v9_4_3_soft_reset()
2451 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2); in gfx_v9_4_3_soft_reset()
2465 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); in gfx_v9_4_3_soft_reset()
2468 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); in gfx_v9_4_3_soft_reset()
2469 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); in gfx_v9_4_3_soft_reset()
2474 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); in gfx_v9_4_3_soft_reset()
2475 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); in gfx_v9_4_3_soft_reset()
2494 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid, in gfx_v9_4_3_ring_emit_gds_switch()
2499 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid, in gfx_v9_4_3_ring_emit_gds_switch()
2504 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid, in gfx_v9_4_3_ring_emit_gds_switch()
2509 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid, in gfx_v9_4_3_ring_emit_gds_switch()
2563 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_update_sram_fgcg()
2572 WREG32_SOC15(GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_update_sram_fgcg()
2585 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_update_repeater_fgcg()
2594 WREG32_SOC15(GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_update_repeater_fgcg()
2607 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); in gfx_v9_4_3_xcc_update_medium_grain_clock_gating()
2615 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v9_4_3_xcc_update_medium_grain_clock_gating()
2621 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); in gfx_v9_4_3_xcc_update_medium_grain_clock_gating()
2624 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); in gfx_v9_4_3_xcc_update_medium_grain_clock_gating()
2628 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); in gfx_v9_4_3_xcc_update_medium_grain_clock_gating()
2631 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); in gfx_v9_4_3_xcc_update_medium_grain_clock_gating()
2636 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); in gfx_v9_4_3_xcc_update_medium_grain_clock_gating()
2644 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v9_4_3_xcc_update_medium_grain_clock_gating()
2647 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); in gfx_v9_4_3_xcc_update_medium_grain_clock_gating()
2650 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); in gfx_v9_4_3_xcc_update_medium_grain_clock_gating()
2654 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); in gfx_v9_4_3_xcc_update_medium_grain_clock_gating()
2657 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); in gfx_v9_4_3_xcc_update_medium_grain_clock_gating()
2671 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); in gfx_v9_4_3_xcc_update_coarse_grain_clock_gating()
2680 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v9_4_3_xcc_update_coarse_grain_clock_gating()
2683 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); in gfx_v9_4_3_xcc_update_coarse_grain_clock_gating()
2692 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); in gfx_v9_4_3_xcc_update_coarse_grain_clock_gating()
2695 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); in gfx_v9_4_3_xcc_update_coarse_grain_clock_gating()
2699 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); in gfx_v9_4_3_xcc_update_coarse_grain_clock_gating()
2701 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); in gfx_v9_4_3_xcc_update_coarse_grain_clock_gating()
2706 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); in gfx_v9_4_3_xcc_update_coarse_grain_clock_gating()
2794 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE)); in gfx_v9_4_3_get_clockgating_state()
2799 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL)); in gfx_v9_4_3_get_clockgating_state()
2808 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL)); in gfx_v9_4_3_get_clockgating_state()
2813 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL)); in gfx_v9_4_3_get_clockgating_state()
2984 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); in gfx_v9_4_3_ring_emit_fence_kiq()
3059 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regSQ_CMD, value); in gfx_v9_4_3_ring_soft_recovery()
3078 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3081 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3084 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3087 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3129 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); in gfx_v9_4_3_get_cpc_int_cntl()
3131 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); in gfx_v9_4_3_get_cpc_int_cntl()
3133 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); in gfx_v9_4_3_get_cpc_int_cntl()
3135 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); in gfx_v9_4_3_get_cpc_int_cntl()
3154 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, in gfx_v9_4_3_set_priv_reg_fault_state()
3194 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, in gfx_v9_4_3_set_bad_op_fault_state()
3233 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, in gfx_v9_4_3_set_priv_inst_fault_state()
3422 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); in gfx_v9_4_3_emit_wave_limit_cs()
3425 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); in gfx_v9_4_3_emit_wave_limit_cs()
3428 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); in gfx_v9_4_3_emit_wave_limit_cs()
3431 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); in gfx_v9_4_3_emit_wave_limit_cs()
3453 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX), in gfx_v9_4_3_emit_wave_limit()
3476 soc15_grbm_select(adev, me, pipe, queue, 0, GET_INST(GC, xcc_id)); in gfx_v9_4_3_unmap_done()
3478 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) in gfx_v9_4_3_unmap_done()
3486 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); in gfx_v9_4_3_unmap_done()
3516 reset_pipe = RREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL); in gfx_v9_4_3_reset_hw_pipe()
3549 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, reset_pipe); in gfx_v9_4_3_reset_hw_pipe()
3550 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, clean_pipe); in gfx_v9_4_3_reset_hw_pipe()
4249 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH),
4252 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI),
4255 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI),
4258 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI),
4261 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI),
4264 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI),
4267 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI),
4270 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI),
4273 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI),
4276 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI),
4279 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI),
4282 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI),
4285 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI),
4288 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI),
4291 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG),
4294 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG),
4297 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI),
4300 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI),
4303 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI),
4309 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH),
4312 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI),
4315 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI),
4318 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI),
4321 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI),
4324 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI),
4327 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI),
4330 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI),
4333 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI),
4336 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI),
4339 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI),
4342 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI),
4345 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI),
4348 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI),
4351 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG),
4354 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG),
4357 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI),
4360 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI),
4363 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI),
4366 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI),
4399 GET_INST(GC, xcc_id), in gfx_v9_4_3_inst_query_ras_err_count()
4408 GET_INST(GC, xcc_id), in gfx_v9_4_3_inst_query_ras_err_count()
4429 GET_INST(GC, xcc_id), in gfx_v9_4_3_inst_query_ras_err_count()
4465 GET_INST(GC, xcc_id)); in gfx_v9_4_3_inst_reset_ras_err_count()
4470 GET_INST(GC, xcc_id)); in gfx_v9_4_3_inst_reset_ras_err_count()
4487 GET_INST(GC, xcc_id)); in gfx_v9_4_3_inst_reset_ras_err_count()
4506 data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG); in gfx_v9_4_3_inst_enable_watchdog_timer()
4522 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data); in gfx_v9_4_3_inst_enable_watchdog_timer()
4648 GET_INST(GC, xcc_id))); in gfx_v9_4_3_ip_dump()
4667 GET_INST(GC, xcc_id)); in gfx_v9_4_3_ip_dump()
4675 RREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_ip_dump()
4683 GET_INST(GC, xcc_id))); in gfx_v9_4_3_ip_dump()
4872 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data); in gfx_v9_4_3_set_user_cu_inactive_bitmap()
4879 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG); in gfx_v9_4_3_get_cu_active_bitmap()
4880 data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG); in gfx_v9_4_3_get_cu_active_bitmap()
4947 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG); in gfx_v9_4_3_get_cu_info()
4950 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG, tmp); in gfx_v9_4_3_get_cu_info()