Lines Matching refs:mec
612 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); in gfx_v9_4_3_mec_fini()
613 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); in gfx_v9_4_3_mec_fini()
640 &adev->gfx.mec.hpd_eop_obj, in gfx_v9_4_3_mec_init()
641 &adev->gfx.mec.hpd_eop_gpu_addr, in gfx_v9_4_3_mec_init()
659 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); in gfx_v9_4_3_mec_init()
660 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v9_4_3_mec_init()
672 &adev->gfx.mec.mec_fw_obj, in gfx_v9_4_3_mec_init()
673 &adev->gfx.mec.mec_fw_gpu_addr, in gfx_v9_4_3_mec_init()
683 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); in gfx_v9_4_3_mec_init()
684 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); in gfx_v9_4_3_mec_init()
971 int xcc_id, int mec, int pipe, int queue) in gfx_v9_4_3_compute_ring_init() argument
983 ring->me = mec + 1; in gfx_v9_4_3_compute_ring_init()
992 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + in gfx_v9_4_3_compute_ring_init()
1000 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) in gfx_v9_4_3_compute_ring_init()
1026 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v9_4_3_alloc_ip_dump()
1027 adev->gfx.mec.num_queue_per_pipe; in gfx_v9_4_3_alloc_ip_dump()
1062 adev->gfx.mec.num_mec = 2; in gfx_v9_4_3_sw_init()
1063 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v9_4_3_sw_init()
1064 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v9_4_3_sw_init()
1109 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v9_4_3_sw_init()
1110 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v9_4_3_sw_init()
1111 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; in gfx_v9_4_3_sw_init()
1776 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); in gfx_v9_4_3_xcc_cp_compute_load_microcode()
1778 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); in gfx_v9_4_3_xcc_cp_compute_load_microcode()
2165 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; in gfx_v9_4_3_xcc_kcq_init_queue()
2178 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v9_4_3_xcc_kcq_init_queue()
2179 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); in gfx_v9_4_3_xcc_kcq_init_queue()
2182 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v9_4_3_xcc_kcq_init_queue()
2183 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); in gfx_v9_4_3_xcc_kcq_init_queue()
3157 for (j = 0; j < adev->gfx.mec.num_mec; j++) { in gfx_v9_4_3_set_priv_reg_fault_state()
3158 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v9_4_3_set_priv_reg_fault_state()
3197 for (j = 0; j < adev->gfx.mec.num_mec; j++) { in gfx_v9_4_3_set_bad_op_fault_state()
3198 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v9_4_3_set_bad_op_fault_state()
3461 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { in gfx_v9_4_3_emit_wave_limit()
4587 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v9_4_3_ip_print()
4588 adev->gfx.mec.num_queue_per_pipe; in gfx_v9_4_3_ip_print()
4593 adev->gfx.mec.num_mec, in gfx_v9_4_3_ip_print()
4594 adev->gfx.mec.num_pipe_per_mec, in gfx_v9_4_3_ip_print()
4595 adev->gfx.mec.num_queue_per_pipe); in gfx_v9_4_3_ip_print()
4600 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v9_4_3_ip_print()
4601 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v9_4_3_ip_print()
4602 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v9_4_3_ip_print()
4655 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v9_4_3_ip_dump()
4656 adev->gfx.mec.num_queue_per_pipe; in gfx_v9_4_3_ip_dump()
4662 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v9_4_3_ip_dump()
4663 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v9_4_3_ip_dump()
4664 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v9_4_3_ip_dump()