Lines Matching refs:tmp
130 uint32_t tmp; in gfxhub_v1_2_xcc_init_system_aperture_regs() local
176 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL2); in gfxhub_v1_2_xcc_init_system_aperture_regs()
177 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, in gfxhub_v1_2_xcc_init_system_aperture_regs()
179 WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL2, tmp); in gfxhub_v1_2_xcc_init_system_aperture_regs()
199 uint32_t tmp; in gfxhub_v1_2_xcc_init_tlb_regs() local
204 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_MX_L1_TLB_CNTL); in gfxhub_v1_2_xcc_init_tlb_regs()
206 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_2_xcc_init_tlb_regs()
208 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_2_xcc_init_tlb_regs()
210 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_2_xcc_init_tlb_regs()
212 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_2_xcc_init_tlb_regs()
214 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_2_xcc_init_tlb_regs()
216 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); in gfxhub_v1_2_xcc_init_tlb_regs()
218 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v1_2_xcc_init_tlb_regs()
225 uint32_t tmp; in gfxhub_v1_2_xcc_init_cache_regs() local
230 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_CNTL); in gfxhub_v1_2_xcc_init_cache_regs()
231 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v1_2_xcc_init_cache_regs()
232 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in gfxhub_v1_2_xcc_init_cache_regs()
234 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, in gfxhub_v1_2_xcc_init_cache_regs()
236 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); in gfxhub_v1_2_xcc_init_cache_regs()
237 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); in gfxhub_v1_2_xcc_init_cache_regs()
238 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); in gfxhub_v1_2_xcc_init_cache_regs()
239 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL, tmp); in gfxhub_v1_2_xcc_init_cache_regs()
241 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_CNTL2); in gfxhub_v1_2_xcc_init_cache_regs()
242 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v1_2_xcc_init_cache_regs()
243 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gfxhub_v1_2_xcc_init_cache_regs()
244 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL2, tmp); in gfxhub_v1_2_xcc_init_cache_regs()
246 tmp = regVM_L2_CNTL3_DEFAULT; in gfxhub_v1_2_xcc_init_cache_regs()
248 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); in gfxhub_v1_2_xcc_init_cache_regs()
249 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, in gfxhub_v1_2_xcc_init_cache_regs()
252 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); in gfxhub_v1_2_xcc_init_cache_regs()
253 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, in gfxhub_v1_2_xcc_init_cache_regs()
256 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL3, tmp); in gfxhub_v1_2_xcc_init_cache_regs()
258 tmp = regVM_L2_CNTL4_DEFAULT; in gfxhub_v1_2_xcc_init_cache_regs()
261 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1); in gfxhub_v1_2_xcc_init_cache_regs()
262 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1); in gfxhub_v1_2_xcc_init_cache_regs()
264 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); in gfxhub_v1_2_xcc_init_cache_regs()
265 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); in gfxhub_v1_2_xcc_init_cache_regs()
267 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL4, tmp); in gfxhub_v1_2_xcc_init_cache_regs()
274 uint32_t tmp; in gfxhub_v1_2_xcc_enable_system_domain() local
278 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL); in gfxhub_v1_2_xcc_enable_system_domain()
279 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v1_2_xcc_enable_system_domain()
280 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, in gfxhub_v1_2_xcc_enable_system_domain()
282 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE, in gfxhub_v1_2_xcc_enable_system_domain()
284 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, in gfxhub_v1_2_xcc_enable_system_domain()
286 WREG32_SOC15(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL, tmp); in gfxhub_v1_2_xcc_enable_system_domain()
333 uint32_t tmp; in gfxhub_v1_2_xcc_setup_vmid_config() local
346 tmp = RREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
348 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v1_2_xcc_setup_vmid_config()
349 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, in gfxhub_v1_2_xcc_setup_vmid_config()
351 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
353 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
356 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
358 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
360 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
362 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
364 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
366 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
374 tmp = REG_SET_FIELD( in gfxhub_v1_2_xcc_setup_vmid_config()
375 tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
381 i * hub->ctx_distance, tmp); in gfxhub_v1_2_xcc_setup_vmid_config()
449 u32 tmp; in gfxhub_v1_2_xcc_gart_disable() local
460 tmp = RREG32_SOC15(GC, GET_INST(GC, j), regMC_VM_MX_L1_TLB_CNTL); in gfxhub_v1_2_xcc_gart_disable()
461 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v1_2_xcc_gart_disable()
462 tmp = REG_SET_FIELD(tmp, in gfxhub_v1_2_xcc_gart_disable()
466 WREG32_SOC15_RLC(GC, GET_INST(GC, j), regMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v1_2_xcc_gart_disable()
470 tmp = RREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL); in gfxhub_v1_2_xcc_gart_disable()
471 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v1_2_xcc_gart_disable()
472 WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL, tmp); in gfxhub_v1_2_xcc_gart_disable()
490 u32 tmp; in gfxhub_v1_2_xcc_set_fault_enable_default() local
494 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v1_2_xcc_set_fault_enable_default()
495 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
497 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
499 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
501 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
503 tmp = REG_SET_FIELD(tmp, in gfxhub_v1_2_xcc_set_fault_enable_default()
507 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
509 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
511 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
513 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
515 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
517 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
520 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
522 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
525 WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL, tmp); in gfxhub_v1_2_xcc_set_fault_enable_default()