Lines Matching refs:gmc
197 adev->gmc.vm_fault.num_types = 1; in gmc_v10_0_set_irq_funcs()
198 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; in gmc_v10_0_set_irq_funcs()
201 adev->gmc.ecc_irq.num_types = 1; in gmc_v10_0_set_irq_funcs()
202 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs; in gmc_v10_0_set_irq_funcs()
283 spin_lock(&adev->gmc.invalidate_lock); in gmc_v10_0_flush_gpu_tlb()
329 spin_unlock(&adev->gmc.invalidate_lock); in gmc_v10_0_flush_gpu_tlb()
494 if (!adev->gmc.translate_further) in gmc_v10_0_get_vm_pde()
574 if (adev->gmc.gmc_funcs == NULL) in gmc_v10_0_set_gmc_funcs()
575 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; in gmc_v10_0_set_gmc_funcs()
639 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; in gmc_v10_0_early_init()
640 adev->gmc.shared_aperture_end = in gmc_v10_0_early_init()
641 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; in gmc_v10_0_early_init()
642 adev->gmc.private_aperture_start = 0x1000000000000000ULL; in gmc_v10_0_early_init()
643 adev->gmc.private_aperture_end = in gmc_v10_0_early_init()
644 adev->gmc.private_aperture_start + (4ULL << 30) - 1; in gmc_v10_0_early_init()
645 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; in gmc_v10_0_early_init()
663 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); in gmc_v10_0_late_init()
674 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; in gmc_v10_0_vram_gtt_location()
677 amdgpu_gmc_vram_location(adev, &adev->gmc, base); in gmc_v10_0_vram_gtt_location()
687 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; in gmc_v10_0_vram_gtt_location()
704 adev->gmc.mc_vram_size = in gmc_v10_0_mc_init()
706 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; in gmc_v10_0_mc_init()
713 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); in gmc_v10_0_mc_init()
714 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); in gmc_v10_0_mc_init()
718 adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev); in gmc_v10_0_mc_init()
719 adev->gmc.aper_size = adev->gmc.real_vram_size; in gmc_v10_0_mc_init()
723 adev->gmc.visible_vram_size = adev->gmc.aper_size; in gmc_v10_0_mc_init()
729 adev->gmc.gart_size = 512ULL << 20; in gmc_v10_0_mc_init()
735 adev->gmc.gart_size = 1024ULL << 20; in gmc_v10_0_mc_init()
739 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; in gmc_v10_0_mc_init()
742 gmc_v10_0_vram_gtt_location(adev, &adev->gmc); in gmc_v10_0_mc_init()
777 spin_lock_init(&adev->gmc.invalidate_lock); in gmc_v10_0_sw_init()
780 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; in gmc_v10_0_sw_init()
781 adev->gmc.vram_width = 64; in gmc_v10_0_sw_init()
783 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6; in gmc_v10_0_sw_init()
784 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */ in gmc_v10_0_sw_init()
788 adev->gmc.vram_width = vram_width; in gmc_v10_0_sw_init()
790 adev->gmc.vram_type = vram_type; in gmc_v10_0_sw_init()
791 adev->gmc.vram_vendor = vram_vendor; in gmc_v10_0_sw_init()
796 adev->gmc.mall_size = 128 * 1024 * 1024; in gmc_v10_0_sw_init()
799 adev->gmc.mall_size = 96 * 1024 * 1024; in gmc_v10_0_sw_init()
802 adev->gmc.mall_size = 32 * 1024 * 1024; in gmc_v10_0_sw_init()
805 adev->gmc.mall_size = 16 * 1024 * 1024; in gmc_v10_0_sw_init()
808 adev->gmc.mall_size = 0; in gmc_v10_0_sw_init()
842 &adev->gmc.vm_fault); in gmc_v10_0_sw_init()
849 &adev->gmc.vm_fault); in gmc_v10_0_sw_init()
856 &adev->gmc.ecc_irq); in gmc_v10_0_sw_init()
865 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ in gmc_v10_0_sw_init()
978 (unsigned int)(adev->gmc.gart_size >> 20), in gmc_v10_0_gart_enable()
989 adev->gmc.flush_pasid_uses_kiq = !amdgpu_emu_mode; in gmc_v10_0_hw_init()
1043 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); in gmc_v10_0_hw_fini()
1045 if (adev->gmc.ecc_irq.funcs && in gmc_v10_0_hw_fini()
1047 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); in gmc_v10_0_hw_fini()