Lines Matching refs:vmid
164 entry->src_id, entry->ring_id, entry->vmid, entry->pasid); in gmc_v10_0_process_interrupt()
222 uint8_t vmid, uint16_t *p_pasid) in gmc_v10_0_get_atc_vmid_pasid_mapping_info() argument
227 + vmid); in gmc_v10_0_get_atc_vmid_pasid_mapping_info()
250 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, in gmc_v10_0_flush_gpu_tlb() argument
255 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); in gmc_v10_0_flush_gpu_tlb()
276 1 << vmid, GET_INST(GC, 0)); in gmc_v10_0_flush_gpu_tlb()
318 tmp &= 1 << vmid; in gmc_v10_0_flush_gpu_tlb()
352 int vmid, i; in gmc_v10_0_flush_gpu_tlb_pasid() local
354 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { in gmc_v10_0_flush_gpu_tlb_pasid()
357 valid = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid, in gmc_v10_0_flush_gpu_tlb_pasid()
365 gmc_v10_0_flush_gpu_tlb(adev, vmid, i, in gmc_v10_0_flush_gpu_tlb_pasid()
368 gmc_v10_0_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), in gmc_v10_0_flush_gpu_tlb_pasid()
375 unsigned int vmid, uint64_t pd_addr) in gmc_v10_0_emit_flush_gpu_tlb() argument
379 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); in gmc_v10_0_emit_flush_gpu_tlb()
397 (hub->ctx_addr_distance * vmid), in gmc_v10_0_emit_flush_gpu_tlb()
401 (hub->ctx_addr_distance * vmid), in gmc_v10_0_emit_flush_gpu_tlb()
408 req, 1 << vmid); in gmc_v10_0_emit_flush_gpu_tlb()
422 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, in gmc_v10_0_emit_pasid_mapping() argument
429 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; in gmc_v10_0_emit_pasid_mapping()
431 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; in gmc_v10_0_emit_pasid_mapping()