Lines Matching refs:vmid
134 entry->src_id, entry->ring_id, entry->vmid, entry->pasid); in gmc_v11_0_process_interrupt()
191 uint8_t vmid, uint16_t *p_pasid) in gmc_v11_0_get_vmid_pasid_mapping_info() argument
193 *p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff; in gmc_v11_0_get_vmid_pasid_mapping_info()
208 static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, in gmc_v11_0_flush_gpu_tlb() argument
213 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); in gmc_v11_0_flush_gpu_tlb()
237 1 << vmid, GET_INST(GC, 0)); in gmc_v11_0_flush_gpu_tlb()
271 tmp &= 1 << vmid; in gmc_v11_0_flush_gpu_tlb()
317 int vmid, i; in gmc_v11_0_flush_gpu_tlb_pasid() local
319 for (vmid = 1; vmid < 16; vmid++) { in gmc_v11_0_flush_gpu_tlb_pasid()
322 valid = gmc_v11_0_get_vmid_pasid_mapping_info(adev, vmid, in gmc_v11_0_flush_gpu_tlb_pasid()
330 gmc_v11_0_flush_gpu_tlb(adev, vmid, i, in gmc_v11_0_flush_gpu_tlb_pasid()
333 gmc_v11_0_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), in gmc_v11_0_flush_gpu_tlb_pasid()
340 unsigned int vmid, uint64_t pd_addr) in gmc_v11_0_emit_flush_gpu_tlb() argument
344 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); in gmc_v11_0_emit_flush_gpu_tlb()
362 (hub->ctx_addr_distance * vmid), in gmc_v11_0_emit_flush_gpu_tlb()
366 (hub->ctx_addr_distance * vmid), in gmc_v11_0_emit_flush_gpu_tlb()
373 req, 1 << vmid); in gmc_v11_0_emit_flush_gpu_tlb()
387 static void gmc_v11_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, in gmc_v11_0_emit_pasid_mapping() argument
394 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid; in gmc_v11_0_emit_pasid_mapping()
396 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid; in gmc_v11_0_emit_pasid_mapping()