Lines Matching refs:WREG32
78 WREG32(mmBIF_FB_EN, 0); in gmc_v6_0_mc_stop()
82 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); in gmc_v6_0_mc_stop()
96 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); in gmc_v6_0_mc_resume()
100 WREG32(mmBIF_FB_EN, tmp); in gmc_v6_0_mc_resume()
173 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v6_0_mc_load_microcode()
174 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v6_0_mc_load_microcode()
178 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); in gmc_v6_0_mc_load_microcode()
179 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); in gmc_v6_0_mc_load_microcode()
183 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); in gmc_v6_0_mc_load_microcode()
186 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v6_0_mc_load_microcode()
187 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); in gmc_v6_0_mc_load_microcode()
188 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); in gmc_v6_0_mc_load_microcode()
227 WREG32((0xb05 + j), 0x00000000); in gmc_v6_0_mc_program()
228 WREG32((0xb06 + j), 0x00000000); in gmc_v6_0_mc_program()
229 WREG32((0xb07 + j), 0x00000000); in gmc_v6_0_mc_program()
230 WREG32((0xb08 + j), 0x00000000); in gmc_v6_0_mc_program()
231 WREG32((0xb09 + j), 0x00000000); in gmc_v6_0_mc_program()
233 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); in gmc_v6_0_mc_program()
248 WREG32(mmVGA_HDP_CONTROL, tmp); in gmc_v6_0_mc_program()
253 WREG32(mmVGA_RENDER_CONTROL, tmp); in gmc_v6_0_mc_program()
256 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, in gmc_v6_0_mc_program()
258 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in gmc_v6_0_mc_program()
260 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, in gmc_v6_0_mc_program()
262 WREG32(mmMC_VM_AGP_BASE, 0); in gmc_v6_0_mc_program()
263 WREG32(mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 22); in gmc_v6_0_mc_program()
264 WREG32(mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 22); in gmc_v6_0_mc_program()
357 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); in gmc_v6_0_flush_gpu_tlb()
410 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v6_0_set_fault_enable_default()
441 WREG32(mmVM_PRT_CNTL, tmp); in gmc_v6_0_set_prt()
449 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); in gmc_v6_0_set_prt()
450 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); in gmc_v6_0_set_prt()
451 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); in gmc_v6_0_set_prt()
452 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); in gmc_v6_0_set_prt()
453 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); in gmc_v6_0_set_prt()
454 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); in gmc_v6_0_set_prt()
455 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); in gmc_v6_0_set_prt()
456 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); in gmc_v6_0_set_prt()
458 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); in gmc_v6_0_set_prt()
459 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); in gmc_v6_0_set_prt()
460 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); in gmc_v6_0_set_prt()
461 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); in gmc_v6_0_set_prt()
462 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); in gmc_v6_0_set_prt()
463 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); in gmc_v6_0_set_prt()
464 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); in gmc_v6_0_set_prt()
465 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); in gmc_v6_0_set_prt()
484 WREG32(mmMC_VM_MX_L1_TLB_CNTL, in gmc_v6_0_gart_enable()
492 WREG32(mmVM_L2_CNTL, in gmc_v6_0_gart_enable()
499 WREG32(mmVM_L2_CNTL2, in gmc_v6_0_gart_enable()
504 WREG32(mmVM_L2_CNTL3, in gmc_v6_0_gart_enable()
509 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); in gmc_v6_0_gart_enable()
510 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); in gmc_v6_0_gart_enable()
511 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12); in gmc_v6_0_gart_enable()
512 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, in gmc_v6_0_gart_enable()
514 WREG32(mmVM_CONTEXT0_CNTL2, 0); in gmc_v6_0_gart_enable()
515 WREG32(mmVM_CONTEXT0_CNTL, in gmc_v6_0_gart_enable()
520 WREG32(0x575, 0); in gmc_v6_0_gart_enable()
521 WREG32(0x576, 0); in gmc_v6_0_gart_enable()
522 WREG32(0x577, 0); in gmc_v6_0_gart_enable()
526 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); in gmc_v6_0_gart_enable()
527 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v6_0_gart_enable()
534 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, in gmc_v6_0_gart_enable()
537 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, in gmc_v6_0_gart_enable()
542 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, in gmc_v6_0_gart_enable()
544 WREG32(mmVM_CONTEXT1_CNTL2, 4); in gmc_v6_0_gart_enable()
545 WREG32(mmVM_CONTEXT1_CNTL, in gmc_v6_0_gart_enable()
592 WREG32(mmVM_CONTEXT0_CNTL, 0); in gmc_v6_0_gart_disable()
593 WREG32(mmVM_CONTEXT1_CNTL, 0); in gmc_v6_0_gart_disable()
595 WREG32(mmMC_VM_MX_L1_TLB_CNTL, in gmc_v6_0_gart_disable()
599 WREG32(mmVM_L2_CNTL, in gmc_v6_0_gart_disable()
604 WREG32(mmVM_L2_CNTL2, 0); in gmc_v6_0_gart_disable()
605 WREG32(mmVM_L2_CNTL3, in gmc_v6_0_gart_disable()
679 WREG32(mc_cg_registers[i], data); in gmc_v6_0_enable_mc_ls()
696 WREG32(mc_cg_registers[i], data); in gmc_v6_0_enable_mc_mgcg()
736 WREG32(mmHDP_HOST_PATH_CNTL, data); in gmc_v6_0_enable_hdp_mgcg()
752 WREG32(mmHDP_MEM_POWER_LS, data); in gmc_v6_0_enable_hdp_ls()
1012 WREG32(mmSRBM_SOFT_RESET, tmp); in gmc_v6_0_soft_reset()
1018 WREG32(mmSRBM_SOFT_RESET, tmp); in gmc_v6_0_soft_reset()
1047 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v6_0_vm_fault_interrupt_state()
1050 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v6_0_vm_fault_interrupt_state()
1055 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v6_0_vm_fault_interrupt_state()
1058 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v6_0_vm_fault_interrupt_state()