Lines Matching refs:gmc
134 err = amdgpu_ucode_request(adev, &adev->gmc.fw, AMDGPU_UCODE_REQUIRED, in gmc_v6_0_init_microcode()
140 amdgpu_ucode_release(&adev->gmc.fw); in gmc_v6_0_init_microcode()
153 if (!adev->gmc.fw) in gmc_v6_0_mc_load_microcode()
156 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v6_0_mc_load_microcode()
160 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); in gmc_v6_0_mc_load_microcode()
163 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); in gmc_v6_0_mc_load_microcode()
166 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gmc_v6_0_mc_load_microcode()
257 adev->gmc.vram_start >> 12); in gmc_v6_0_mc_program()
259 adev->gmc.vram_end >> 12); in gmc_v6_0_mc_program()
263 WREG32(mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 22); in gmc_v6_0_mc_program()
264 WREG32(mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 22); in gmc_v6_0_mc_program()
316 adev->gmc.vram_width = numchan * chansize; in gmc_v6_0_mc_init()
318 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; in gmc_v6_0_mc_init()
319 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; in gmc_v6_0_mc_init()
326 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); in gmc_v6_0_mc_init()
327 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); in gmc_v6_0_mc_init()
328 adev->gmc.visible_vram_size = adev->gmc.aper_size; in gmc_v6_0_mc_init()
335 adev->gmc.gart_size = 256ULL << 20; in gmc_v6_0_mc_init()
341 adev->gmc.gart_size = 1024ULL << 20; in gmc_v6_0_mc_init()
345 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; in gmc_v6_0_mc_init()
348 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; in gmc_v6_0_mc_init()
349 gmc_v6_0_vram_gtt_location(adev, &adev->gmc); in gmc_v6_0_mc_init()
423 if (enable && !adev->gmc.prt_warning) { in gmc_v6_0_set_prt()
425 adev->gmc.prt_warning = true; in gmc_v6_0_set_prt()
509 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); in gmc_v6_0_gart_enable()
510 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); in gmc_v6_0_gart_enable()
557 (unsigned int)(adev->gmc.gart_size >> 20), in gmc_v6_0_gart_enable()
790 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); in gmc_v6_0_late_init()
820 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; in gmc_v6_0_sw_init()
825 adev->gmc.vram_type = gmc_v6_0_convert_vram_type(tmp); in gmc_v6_0_sw_init()
828 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault); in gmc_v6_0_sw_init()
832 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault); in gmc_v6_0_sw_init()
838 adev->gmc.mc_mask = 0xffffffffffULL; in gmc_v6_0_sw_init()
897 amdgpu_ucode_release(&adev->gmc.fw); in gmc_v6_0_sw_fini()
931 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); in gmc_v6_0_hw_fini()
1155 adev->gmc.gmc_funcs = &gmc_v6_0_gmc_funcs; in gmc_v6_0_set_gmc_funcs()
1160 adev->gmc.vm_fault.num_types = 1; in gmc_v6_0_set_irq_funcs()
1161 adev->gmc.vm_fault.funcs = &gmc_v6_0_irq_funcs; in gmc_v6_0_set_irq_funcs()