Lines Matching refs:WREG32
102 WREG32(mmBIF_FB_EN, 0); in gmc_v7_0_mc_stop()
106 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); in gmc_v7_0_mc_stop()
119 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); in gmc_v7_0_mc_resume()
123 WREG32(mmBIF_FB_EN, tmp); in gmc_v7_0_mc_resume()
203 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v7_0_mc_load_microcode()
204 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v7_0_mc_load_microcode()
208 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); in gmc_v7_0_mc_load_microcode()
209 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); in gmc_v7_0_mc_load_microcode()
213 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); in gmc_v7_0_mc_load_microcode()
216 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v7_0_mc_load_microcode()
217 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); in gmc_v7_0_mc_load_microcode()
218 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); in gmc_v7_0_mc_load_microcode()
270 WREG32((0xb05 + j), 0x00000000); in gmc_v7_0_mc_program()
271 WREG32((0xb06 + j), 0x00000000); in gmc_v7_0_mc_program()
272 WREG32((0xb07 + j), 0x00000000); in gmc_v7_0_mc_program()
273 WREG32((0xb08 + j), 0x00000000); in gmc_v7_0_mc_program()
274 WREG32((0xb09 + j), 0x00000000); in gmc_v7_0_mc_program()
276 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); in gmc_v7_0_mc_program()
285 WREG32(mmVGA_HDP_CONTROL, tmp); in gmc_v7_0_mc_program()
290 WREG32(mmVGA_RENDER_CONTROL, tmp); in gmc_v7_0_mc_program()
293 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, in gmc_v7_0_mc_program()
295 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in gmc_v7_0_mc_program()
297 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, in gmc_v7_0_mc_program()
299 WREG32(mmMC_VM_AGP_BASE, 0); in gmc_v7_0_mc_program()
300 WREG32(mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 22); in gmc_v7_0_mc_program()
301 WREG32(mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 22); in gmc_v7_0_mc_program()
305 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); in gmc_v7_0_mc_program()
309 WREG32(mmHDP_MISC_CNTL, tmp); in gmc_v7_0_mc_program()
312 WREG32(mmHDP_HOST_PATH_CNTL, tmp); in gmc_v7_0_mc_program()
449 WREG32(mmVM_INVALIDATE_REQUEST, mask); in gmc_v7_0_flush_gpu_tlb_pasid()
474 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); in gmc_v7_0_flush_gpu_tlb()
538 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v7_0_set_fault_enable_default()
571 WREG32(mmVM_PRT_CNTL, tmp); in gmc_v7_0_set_prt()
579 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); in gmc_v7_0_set_prt()
580 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); in gmc_v7_0_set_prt()
581 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); in gmc_v7_0_set_prt()
582 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); in gmc_v7_0_set_prt()
583 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); in gmc_v7_0_set_prt()
584 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); in gmc_v7_0_set_prt()
585 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); in gmc_v7_0_set_prt()
586 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); in gmc_v7_0_set_prt()
588 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); in gmc_v7_0_set_prt()
589 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); in gmc_v7_0_set_prt()
590 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); in gmc_v7_0_set_prt()
591 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); in gmc_v7_0_set_prt()
592 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); in gmc_v7_0_set_prt()
593 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); in gmc_v7_0_set_prt()
594 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); in gmc_v7_0_set_prt()
595 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); in gmc_v7_0_set_prt()
630 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); in gmc_v7_0_gart_enable()
640 WREG32(mmVM_L2_CNTL, tmp); in gmc_v7_0_gart_enable()
643 WREG32(mmVM_L2_CNTL2, tmp); in gmc_v7_0_gart_enable()
650 WREG32(mmVM_L2_CNTL3, tmp); in gmc_v7_0_gart_enable()
652 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); in gmc_v7_0_gart_enable()
653 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); in gmc_v7_0_gart_enable()
654 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12); in gmc_v7_0_gart_enable()
655 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, in gmc_v7_0_gart_enable()
657 WREG32(mmVM_CONTEXT0_CNTL2, 0); in gmc_v7_0_gart_enable()
662 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v7_0_gart_enable()
664 WREG32(0x575, 0); in gmc_v7_0_gart_enable()
665 WREG32(0x576, 0); in gmc_v7_0_gart_enable()
666 WREG32(0x577, 0); in gmc_v7_0_gart_enable()
673 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); in gmc_v7_0_gart_enable()
674 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v7_0_gart_enable()
677 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, in gmc_v7_0_gart_enable()
680 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, in gmc_v7_0_gart_enable()
685 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, in gmc_v7_0_gart_enable()
687 WREG32(mmVM_CONTEXT1_CNTL2, 4); in gmc_v7_0_gart_enable()
693 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v7_0_gart_enable()
702 WREG32(mmCHUB_CONTROL, tmp); in gmc_v7_0_gart_enable()
741 WREG32(mmVM_CONTEXT0_CNTL, 0); in gmc_v7_0_gart_disable()
742 WREG32(mmVM_CONTEXT1_CNTL, 0); in gmc_v7_0_gart_disable()
748 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); in gmc_v7_0_gart_disable()
752 WREG32(mmVM_L2_CNTL, tmp); in gmc_v7_0_gart_disable()
753 WREG32(mmVM_L2_CNTL2, 0); in gmc_v7_0_gart_disable()
837 WREG32(mc_cg_registers[i], data); in gmc_v7_0_enable_mc_ls()
854 WREG32(mc_cg_registers[i], data); in gmc_v7_0_enable_mc_mgcg()
894 WREG32(mmHDP_HOST_PATH_CNTL, data); in gmc_v7_0_enable_hdp_mgcg()
910 WREG32(mmHDP_MEM_POWER_LS, data); in gmc_v7_0_enable_hdp_ls()
1196 WREG32(mmSRBM_SOFT_RESET, tmp); in gmc_v7_0_soft_reset()
1202 WREG32(mmSRBM_SOFT_RESET, tmp); in gmc_v7_0_soft_reset()
1233 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v7_0_vm_fault_interrupt_state()
1237 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v7_0_vm_fault_interrupt_state()
1243 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v7_0_vm_fault_interrupt_state()
1247 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v7_0_vm_fault_interrupt_state()