Lines Matching refs:WREG32
184 WREG32(mmBIF_FB_EN, 0); in gmc_v8_0_mc_stop()
188 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout); in gmc_v8_0_mc_stop()
201 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); in gmc_v8_0_mc_resume()
205 WREG32(mmBIF_FB_EN, tmp); in gmc_v8_0_mc_resume()
245 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, ixMC_IO_DEBUG_UP_159); in gmc_v8_0_init_microcode()
313 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_tonga_mc_load_microcode()
314 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v8_0_tonga_mc_load_microcode()
318 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); in gmc_v8_0_tonga_mc_load_microcode()
319 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); in gmc_v8_0_tonga_mc_load_microcode()
323 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); in gmc_v8_0_tonga_mc_load_microcode()
326 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_tonga_mc_load_microcode()
327 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); in gmc_v8_0_tonga_mc_load_microcode()
328 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); in gmc_v8_0_tonga_mc_load_microcode()
380 WREG32(mmMC_SEQ_MISC0, data); in gmc_v8_0_polaris_mc_load_microcode()
384 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); in gmc_v8_0_polaris_mc_load_microcode()
385 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); in gmc_v8_0_polaris_mc_load_microcode()
388 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_polaris_mc_load_microcode()
389 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v8_0_polaris_mc_load_microcode()
393 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); in gmc_v8_0_polaris_mc_load_microcode()
396 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_polaris_mc_load_microcode()
397 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); in gmc_v8_0_polaris_mc_load_microcode()
398 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); in gmc_v8_0_polaris_mc_load_microcode()
441 WREG32((0xb05 + j), 0x00000000); in gmc_v8_0_mc_program()
442 WREG32((0xb06 + j), 0x00000000); in gmc_v8_0_mc_program()
443 WREG32((0xb07 + j), 0x00000000); in gmc_v8_0_mc_program()
444 WREG32((0xb08 + j), 0x00000000); in gmc_v8_0_mc_program()
445 WREG32((0xb09 + j), 0x00000000); in gmc_v8_0_mc_program()
447 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); in gmc_v8_0_mc_program()
460 WREG32(mmVGA_HDP_CONTROL, tmp); in gmc_v8_0_mc_program()
465 WREG32(mmVGA_RENDER_CONTROL, tmp); in gmc_v8_0_mc_program()
468 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, in gmc_v8_0_mc_program()
470 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in gmc_v8_0_mc_program()
472 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, in gmc_v8_0_mc_program()
478 WREG32(mmMC_VM_FB_LOCATION, tmp); in gmc_v8_0_mc_program()
480 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); in gmc_v8_0_mc_program()
481 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); in gmc_v8_0_mc_program()
482 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); in gmc_v8_0_mc_program()
485 WREG32(mmMC_VM_AGP_BASE, 0); in gmc_v8_0_mc_program()
486 WREG32(mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 22); in gmc_v8_0_mc_program()
487 WREG32(mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 22); in gmc_v8_0_mc_program()
491 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); in gmc_v8_0_mc_program()
495 WREG32(mmHDP_MISC_CNTL, tmp); in gmc_v8_0_mc_program()
498 WREG32(mmHDP_HOST_PATH_CNTL, tmp); in gmc_v8_0_mc_program()
640 WREG32(mmVM_INVALIDATE_REQUEST, mask); in gmc_v8_0_flush_gpu_tlb_pasid()
665 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); in gmc_v8_0_flush_gpu_tlb()
753 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_set_fault_enable_default()
786 WREG32(mmVM_PRT_CNTL, tmp); in gmc_v8_0_set_prt()
794 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); in gmc_v8_0_set_prt()
795 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); in gmc_v8_0_set_prt()
796 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); in gmc_v8_0_set_prt()
797 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); in gmc_v8_0_set_prt()
798 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); in gmc_v8_0_set_prt()
799 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); in gmc_v8_0_set_prt()
800 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); in gmc_v8_0_set_prt()
801 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); in gmc_v8_0_set_prt()
803 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); in gmc_v8_0_set_prt()
804 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); in gmc_v8_0_set_prt()
805 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); in gmc_v8_0_set_prt()
806 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); in gmc_v8_0_set_prt()
807 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); in gmc_v8_0_set_prt()
808 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); in gmc_v8_0_set_prt()
809 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); in gmc_v8_0_set_prt()
810 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); in gmc_v8_0_set_prt()
845 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); in gmc_v8_0_gart_enable()
855 WREG32(mmVM_L2_CNTL, tmp); in gmc_v8_0_gart_enable()
859 WREG32(mmVM_L2_CNTL2, tmp); in gmc_v8_0_gart_enable()
866 WREG32(mmVM_L2_CNTL3, tmp); in gmc_v8_0_gart_enable()
881 WREG32(mmVM_L2_CNTL4, tmp); in gmc_v8_0_gart_enable()
883 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); in gmc_v8_0_gart_enable()
884 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); in gmc_v8_0_gart_enable()
885 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12); in gmc_v8_0_gart_enable()
886 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, in gmc_v8_0_gart_enable()
888 WREG32(mmVM_CONTEXT0_CNTL2, 0); in gmc_v8_0_gart_enable()
893 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v8_0_gart_enable()
895 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0); in gmc_v8_0_gart_enable()
896 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0); in gmc_v8_0_gart_enable()
897 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0); in gmc_v8_0_gart_enable()
904 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); in gmc_v8_0_gart_enable()
905 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v8_0_gart_enable()
908 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, in gmc_v8_0_gart_enable()
911 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, in gmc_v8_0_gart_enable()
916 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, in gmc_v8_0_gart_enable()
918 WREG32(mmVM_CONTEXT1_CNTL2, 4); in gmc_v8_0_gart_enable()
931 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_gart_enable()
973 WREG32(mmVM_CONTEXT0_CNTL, 0); in gmc_v8_0_gart_disable()
974 WREG32(mmVM_CONTEXT1_CNTL, 0); in gmc_v8_0_gart_disable()
980 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); in gmc_v8_0_gart_disable()
984 WREG32(mmVM_L2_CNTL, tmp); in gmc_v8_0_gart_disable()
985 WREG32(mmVM_L2_CNTL2, 0); in gmc_v8_0_gart_disable()
1356 WREG32(mmSRBM_SOFT_RESET, tmp); in gmc_v8_0_soft_reset()
1362 WREG32(mmSRBM_SOFT_RESET, tmp); in gmc_v8_0_soft_reset()
1402 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v8_0_vm_fault_interrupt_state()
1406 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_vm_fault_interrupt_state()
1412 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v8_0_vm_fault_interrupt_state()
1416 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_vm_fault_interrupt_state()
1508 WREG32(mmMC_HUB_MISC_HUB_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1512 WREG32(mmMC_HUB_MISC_SIP_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1516 WREG32(mmMC_HUB_MISC_VM_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1520 WREG32(mmMC_XPB_CLK_GAT, data); in fiji_update_mc_medium_grain_clock_gating()
1524 WREG32(mmATC_MISC_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1528 WREG32(mmMC_CITF_MISC_WR_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1532 WREG32(mmMC_CITF_MISC_RD_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1536 WREG32(mmMC_CITF_MISC_VM_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1540 WREG32(mmVM_L2_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1544 WREG32(mmMC_HUB_MISC_HUB_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1548 WREG32(mmMC_HUB_MISC_SIP_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1552 WREG32(mmMC_HUB_MISC_VM_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1556 WREG32(mmMC_XPB_CLK_GAT, data); in fiji_update_mc_medium_grain_clock_gating()
1560 WREG32(mmATC_MISC_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1564 WREG32(mmMC_CITF_MISC_WR_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1568 WREG32(mmMC_CITF_MISC_RD_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1572 WREG32(mmMC_CITF_MISC_VM_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1576 WREG32(mmVM_L2_CG, data); in fiji_update_mc_medium_grain_clock_gating()
1588 WREG32(mmMC_HUB_MISC_HUB_CG, data); in fiji_update_mc_light_sleep()
1592 WREG32(mmMC_HUB_MISC_SIP_CG, data); in fiji_update_mc_light_sleep()
1596 WREG32(mmMC_HUB_MISC_VM_CG, data); in fiji_update_mc_light_sleep()
1600 WREG32(mmMC_XPB_CLK_GAT, data); in fiji_update_mc_light_sleep()
1604 WREG32(mmATC_MISC_CG, data); in fiji_update_mc_light_sleep()
1608 WREG32(mmMC_CITF_MISC_WR_CG, data); in fiji_update_mc_light_sleep()
1612 WREG32(mmMC_CITF_MISC_RD_CG, data); in fiji_update_mc_light_sleep()
1616 WREG32(mmMC_CITF_MISC_VM_CG, data); in fiji_update_mc_light_sleep()
1620 WREG32(mmVM_L2_CG, data); in fiji_update_mc_light_sleep()
1624 WREG32(mmMC_HUB_MISC_HUB_CG, data); in fiji_update_mc_light_sleep()
1628 WREG32(mmMC_HUB_MISC_SIP_CG, data); in fiji_update_mc_light_sleep()
1632 WREG32(mmMC_HUB_MISC_VM_CG, data); in fiji_update_mc_light_sleep()
1636 WREG32(mmMC_XPB_CLK_GAT, data); in fiji_update_mc_light_sleep()
1640 WREG32(mmATC_MISC_CG, data); in fiji_update_mc_light_sleep()
1644 WREG32(mmMC_CITF_MISC_WR_CG, data); in fiji_update_mc_light_sleep()
1648 WREG32(mmMC_CITF_MISC_RD_CG, data); in fiji_update_mc_light_sleep()
1652 WREG32(mmMC_CITF_MISC_VM_CG, data); in fiji_update_mc_light_sleep()
1656 WREG32(mmVM_L2_CG, data); in fiji_update_mc_light_sleep()