Lines Matching refs:gmc
262 err = amdgpu_ucode_request(adev, &adev->gmc.fw, AMDGPU_UCODE_REQUIRED, in gmc_v8_0_init_microcode()
266 amdgpu_ucode_release(&adev->gmc.fw); in gmc_v8_0_init_microcode()
295 if (!adev->gmc.fw) in gmc_v8_0_tonga_mc_load_microcode()
298 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v8_0_tonga_mc_load_microcode()
301 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); in gmc_v8_0_tonga_mc_load_microcode()
304 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); in gmc_v8_0_tonga_mc_load_microcode()
307 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gmc_v8_0_tonga_mc_load_microcode()
364 if (!adev->gmc.fw) in gmc_v8_0_polaris_mc_load_microcode()
367 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v8_0_polaris_mc_load_microcode()
370 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); in gmc_v8_0_polaris_mc_load_microcode()
373 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); in gmc_v8_0_polaris_mc_load_microcode()
376 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gmc_v8_0_polaris_mc_load_microcode()
469 adev->gmc.vram_start >> 12); in gmc_v8_0_mc_program()
471 adev->gmc.vram_end >> 12); in gmc_v8_0_mc_program()
476 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16; in gmc_v8_0_mc_program()
477 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF); in gmc_v8_0_mc_program()
480 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); in gmc_v8_0_mc_program()
486 WREG32(mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 22); in gmc_v8_0_mc_program()
487 WREG32(mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 22); in gmc_v8_0_mc_program()
515 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev); in gmc_v8_0_mc_init()
516 if (!adev->gmc.vram_width) { in gmc_v8_0_mc_init()
557 adev->gmc.vram_width = numchan * chansize; in gmc_v8_0_mc_init()
567 adev->gmc.mc_vram_size = tmp * 1024ULL * 1024ULL; in gmc_v8_0_mc_init()
568 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; in gmc_v8_0_mc_init()
575 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); in gmc_v8_0_mc_init()
576 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); in gmc_v8_0_mc_init()
580 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; in gmc_v8_0_mc_init()
581 adev->gmc.aper_size = adev->gmc.real_vram_size; in gmc_v8_0_mc_init()
585 adev->gmc.visible_vram_size = adev->gmc.aper_size; in gmc_v8_0_mc_init()
595 adev->gmc.gart_size = 256ULL << 20; in gmc_v8_0_mc_init()
601 adev->gmc.gart_size = 1024ULL << 20; in gmc_v8_0_mc_init()
605 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; in gmc_v8_0_mc_init()
608 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; in gmc_v8_0_mc_init()
609 gmc_v8_0_vram_gtt_location(adev, &adev->gmc); in gmc_v8_0_mc_init()
766 if (enable && !adev->gmc.prt_warning) { in gmc_v8_0_set_prt()
768 adev->gmc.prt_warning = true; in gmc_v8_0_set_prt()
883 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); in gmc_v8_0_gart_enable()
884 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); in gmc_v8_0_gart_enable()
939 (unsigned int)(adev->gmc.gart_size >> 20), in gmc_v8_0_gart_enable()
1048 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; in gmc_v8_0_early_init()
1049 adev->gmc.shared_aperture_end = in gmc_v8_0_early_init()
1050 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; in gmc_v8_0_early_init()
1051 adev->gmc.private_aperture_start = in gmc_v8_0_early_init()
1052 adev->gmc.shared_aperture_end + 1; in gmc_v8_0_early_init()
1053 adev->gmc.private_aperture_end = in gmc_v8_0_early_init()
1054 adev->gmc.private_aperture_start + (4ULL << 30) - 1; in gmc_v8_0_early_init()
1055 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; in gmc_v8_0_early_init()
1065 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); in gmc_v8_0_late_init()
1098 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; in gmc_v8_0_sw_init()
1108 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp); in gmc_v8_0_sw_init()
1111 …_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault); in gmc_v8_0_sw_init()
1115 …_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault); in gmc_v8_0_sw_init()
1129 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ in gmc_v8_0_sw_init()
1178 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info), in gmc_v8_0_sw_init()
1180 if (!adev->gmc.vm_fault_info) in gmc_v8_0_sw_init()
1182 atomic_set(&adev->gmc.vm_fault_info_updated, 0); in gmc_v8_0_sw_init()
1193 kfree(adev->gmc.vm_fault_info); in gmc_v8_0_sw_fini()
1196 amdgpu_ucode_release(&adev->gmc.fw); in gmc_v8_0_sw_fini()
1240 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); in gmc_v8_0_hw_fini()
1318 adev->gmc.srbm_soft_reset = srbm_soft_reset; in gmc_v8_0_check_soft_reset()
1322 adev->gmc.srbm_soft_reset = 0; in gmc_v8_0_check_soft_reset()
1331 if (!adev->gmc.srbm_soft_reset) in gmc_v8_0_pre_soft_reset()
1346 if (!adev->gmc.srbm_soft_reset) in gmc_v8_0_soft_reset()
1348 srbm_soft_reset = adev->gmc.srbm_soft_reset; in gmc_v8_0_soft_reset()
1376 if (!adev->gmc.srbm_soft_reset) in gmc_v8_0_post_soft_reset()
1477 && !atomic_read(&adev->gmc.vm_fault_info_updated)) { in gmc_v8_0_process_interrupt()
1478 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info; in gmc_v8_0_process_interrupt()
1494 atomic_set(&adev->gmc.vm_fault_info_updated, 1); in gmc_v8_0_process_interrupt()
1744 adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs; in gmc_v8_0_set_gmc_funcs()
1749 adev->gmc.vm_fault.num_types = 1; in gmc_v8_0_set_irq_funcs()
1750 adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs; in gmc_v8_0_set_irq_funcs()