Lines Matching refs:reg_offset
42 …_decode_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val) in jpeg_v1_0_decode_ring_patch_wreg() argument
46 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || in jpeg_v1_0_decode_ring_patch_wreg()
47 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { in jpeg_v1_0_decode_ring_patch_wreg()
49 ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0); in jpeg_v1_0_decode_ring_patch_wreg()
51 ring->ring[(*ptr)++] = reg_offset; in jpeg_v1_0_decode_ring_patch_wreg()
61 uint32_t reg, reg_offset, val, mask, i; in jpeg_v1_0_decode_ring_set_patch_ring() local
65 reg_offset = (reg << 2); in jpeg_v1_0_decode_ring_set_patch_ring()
67 jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val); in jpeg_v1_0_decode_ring_set_patch_ring()
71 reg_offset = (reg << 2); in jpeg_v1_0_decode_ring_set_patch_ring()
73 jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val); in jpeg_v1_0_decode_ring_set_patch_ring()
83 reg_offset = (reg << 2); in jpeg_v1_0_decode_ring_set_patch_ring()
85 jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val); in jpeg_v1_0_decode_ring_set_patch_ring()
89 reg_offset = (reg << 2); in jpeg_v1_0_decode_ring_set_patch_ring()
91 jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val); in jpeg_v1_0_decode_ring_set_patch_ring()
95 reg_offset = (reg << 2); in jpeg_v1_0_decode_ring_set_patch_ring()
104 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || in jpeg_v1_0_decode_ring_set_patch_ring()
105 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { in jpeg_v1_0_decode_ring_set_patch_ring()
107 ring->ring[ptr++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3); in jpeg_v1_0_decode_ring_set_patch_ring()
109 ring->ring[ptr++] = reg_offset; in jpeg_v1_0_decode_ring_set_patch_ring()
122 reg_offset = (reg << 2); in jpeg_v1_0_decode_ring_set_patch_ring()
124 jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val); in jpeg_v1_0_decode_ring_set_patch_ring()
128 reg_offset = (reg << 2); in jpeg_v1_0_decode_ring_set_patch_ring()
130 jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val); in jpeg_v1_0_decode_ring_set_patch_ring()
358 uint32_t reg_offset = (reg << 2); in jpeg_v1_0_decode_ring_emit_reg_wait() local
370 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || in jpeg_v1_0_decode_ring_emit_reg_wait()
371 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { in jpeg_v1_0_decode_ring_emit_reg_wait()
374 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); in jpeg_v1_0_decode_ring_emit_reg_wait()
376 amdgpu_ring_write(ring, reg_offset); in jpeg_v1_0_decode_ring_emit_reg_wait()
402 uint32_t reg_offset = (reg << 2); in jpeg_v1_0_decode_ring_emit_wreg() local
406 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || in jpeg_v1_0_decode_ring_emit_wreg()
407 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { in jpeg_v1_0_decode_ring_emit_wreg()
410 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_wreg()
412 amdgpu_ring_write(ring, reg_offset); in jpeg_v1_0_decode_ring_emit_wreg()