Lines Matching refs:jpeg
68 adev->jpeg.num_jpeg_inst = 1; in jpeg_v2_0_early_init()
69 adev->jpeg.num_jpeg_rings = 1; in jpeg_v2_0_early_init()
92 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); in jpeg_v2_0_sw_init()
104 ring = adev->jpeg.inst->ring_dec; in jpeg_v2_0_sw_init()
109 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, in jpeg_v2_0_sw_init()
114 adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; in jpeg_v2_0_sw_init()
115 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH); in jpeg_v2_0_sw_init()
121 adev->jpeg.supported_reset = in jpeg_v2_0_sw_init()
122 amdgpu_get_soft_full_reset_mask(adev->jpeg.inst[0].ring_dec); in jpeg_v2_0_sw_init()
124 adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in jpeg_v2_0_sw_init()
162 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; in jpeg_v2_0_hw_init()
181 cancel_delayed_work_sync(&adev->jpeg.idle_work); in jpeg_v2_0_hw_fini()
183 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && in jpeg_v2_0_hw_fini()
338 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; in jpeg_v2_0_start()
729 if (state == adev->jpeg.cur_state) in jpeg_v2_0_set_powergating_state()
738 adev->jpeg.cur_state = state; in jpeg_v2_0_set_powergating_state()
759 amdgpu_fence_process(adev->jpeg.inst->ring_dec); in jpeg_v2_0_process_interrupt()
836 adev->jpeg.inst->ring_dec->funcs = &jpeg_v2_0_dec_ring_vm_funcs; in jpeg_v2_0_set_dec_ring_funcs()
846 adev->jpeg.inst->irq.num_types = 1; in jpeg_v2_0_set_irq_funcs()
847 adev->jpeg.inst->irq.funcs = &jpeg_v2_0_irq_funcs; in jpeg_v2_0_set_irq_funcs()