Lines Matching refs:jpeg
100 return (adev->jpeg.caps & AMDGPU_JPEG_CAPS(RRMT_ENABLED)) == 0; in jpeg_v4_0_3_normalizn_reqd()
122 adev->jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS_4_0_3; in jpeg_v4_0_3_early_init()
144 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_sw_init()
147 amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq); in jpeg_v4_0_3_sw_init()
154 VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq); in jpeg_v4_0_3_sw_init()
160 VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq); in jpeg_v4_0_3_sw_init()
172 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_sw_init()
175 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_sw_init()
176 ring = &adev->jpeg.inst[i].ring_dec[j]; in jpeg_v4_0_3_sw_init()
178 ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id); in jpeg_v4_0_3_sw_init()
193 sprintf(ring->name, "jpeg_dec_%d.%d", adev->jpeg.inst[i].aid_id, j); in jpeg_v4_0_3_sw_init()
194 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, in jpeg_v4_0_3_sw_init()
199 adev->jpeg.internal.jpeg_pitch[j] = in jpeg_v4_0_3_sw_init()
201 adev->jpeg.inst[i].external.jpeg_pitch[j] = in jpeg_v4_0_3_sw_init()
219 adev->jpeg.supported_reset = in jpeg_v4_0_3_sw_init()
220 amdgpu_get_soft_full_reset_mask(adev->jpeg.inst[0].ring_dec); in jpeg_v4_0_3_sw_init()
222 adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in jpeg_v4_0_3_sw_init()
275 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { in jpeg_v4_0_3_start_sriov()
287 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) { in jpeg_v4_0_3_start_sriov()
288 ring = &adev->jpeg.inst[i].ring_dec[j]; in jpeg_v4_0_3_start_sriov()
381 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_hw_init()
382 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_hw_init()
383 ring = &adev->jpeg.inst[i].ring_dec[j]; in jpeg_v4_0_3_hw_init()
394 adev->jpeg.caps |= AMDGPU_JPEG_CAPS(RRMT_ENABLED); in jpeg_v4_0_3_hw_init()
396 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_hw_init()
399 ring = adev->jpeg.inst[i].ring_dec; in jpeg_v4_0_3_hw_init()
406 adev->jpeg.inst[i].aid_id); in jpeg_v4_0_3_hw_init()
408 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_hw_init()
409 ring = &adev->jpeg.inst[i].ring_dec[j]; in jpeg_v4_0_3_hw_init()
440 cancel_delayed_work_sync(&adev->jpeg.idle_work); in jpeg_v4_0_3_hw_fini()
443 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE) in jpeg_v4_0_3_hw_fini()
448 amdgpu_irq_put(adev, &adev->jpeg.inst->ras_poison_irq, 0); in jpeg_v4_0_3_hw_fini()
513 for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) in jpeg_v4_0_3_disable_clock_gating()
538 for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) in jpeg_v4_0_3_enable_clock_gating()
624 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_start()
626 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_start()
627 ring = &adev->jpeg.inst[i].ring_dec[j]; in jpeg_v4_0_3_start()
663 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) in jpeg_v4_0_3_stop()
976 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_is_idle()
977 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_is_idle()
994 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_wait_for_idle()
995 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_wait_for_idle()
1012 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_set_clockgating_state()
1031 adev->jpeg.cur_state = AMD_PG_STATE_UNGATE; in jpeg_v4_0_3_set_powergating_state()
1035 if (state == adev->jpeg.cur_state) in jpeg_v4_0_3_set_powergating_state()
1044 adev->jpeg.cur_state = state; in jpeg_v4_0_3_set_powergating_state()
1074 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; ++inst) in jpeg_v4_0_3_process_interrupt()
1075 if (adev->jpeg.inst[inst].aid_id == i) in jpeg_v4_0_3_process_interrupt()
1078 if (inst >= adev->jpeg.num_jpeg_inst) { in jpeg_v4_0_3_process_interrupt()
1087 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[0]); in jpeg_v4_0_3_process_interrupt()
1090 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[1]); in jpeg_v4_0_3_process_interrupt()
1093 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[2]); in jpeg_v4_0_3_process_interrupt()
1096 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[3]); in jpeg_v4_0_3_process_interrupt()
1099 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[4]); in jpeg_v4_0_3_process_interrupt()
1102 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[5]); in jpeg_v4_0_3_process_interrupt()
1105 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[6]); in jpeg_v4_0_3_process_interrupt()
1108 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[7]); in jpeg_v4_0_3_process_interrupt()
1210 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_set_dec_ring_funcs()
1211 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_set_dec_ring_funcs()
1212 adev->jpeg.inst[i].ring_dec[j].funcs = &jpeg_v4_0_3_dec_ring_vm_funcs; in jpeg_v4_0_3_set_dec_ring_funcs()
1213 adev->jpeg.inst[i].ring_dec[j].me = i; in jpeg_v4_0_3_set_dec_ring_funcs()
1214 adev->jpeg.inst[i].ring_dec[j].pipe = j; in jpeg_v4_0_3_set_dec_ring_funcs()
1217 adev->jpeg.inst[i].aid_id = in jpeg_v4_0_3_set_dec_ring_funcs()
1218 jpeg_inst / adev->jpeg.num_inst_per_aid; in jpeg_v4_0_3_set_dec_ring_funcs()
1236 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_set_irq_funcs()
1237 adev->jpeg.inst->irq.num_types += adev->jpeg.num_jpeg_rings; in jpeg_v4_0_3_set_irq_funcs()
1239 adev->jpeg.inst->irq.funcs = &jpeg_v4_0_3_irq_funcs; in jpeg_v4_0_3_set_irq_funcs()
1241 adev->jpeg.inst->ras_poison_irq.num_types = 1; in jpeg_v4_0_3_set_irq_funcs()
1242 adev->jpeg.inst->ras_poison_irq.funcs = &jpeg_v4_0_3_ras_irq_funcs; in jpeg_v4_0_3_set_irq_funcs()
1313 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) in jpeg_v4_0_3_query_ras_error_count()
1335 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) in jpeg_v4_0_3_reset_ras_error_count()
1368 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++) in jpeg_v4_0_3_query_ras_poison_status()
1457 adev->jpeg.inst->ras_poison_irq.funcs) { in jpeg_v4_0_3_ras_late_init()
1458 r = amdgpu_irq_get(adev, &adev->jpeg.inst->ras_poison_irq, 0); in jpeg_v4_0_3_ras_late_init()
1485 adev->jpeg.ras = &jpeg_v4_0_3_ras; in jpeg_v4_0_3_set_ras_funcs()