Lines Matching refs:jpeg
69 adev->jpeg.num_jpeg_inst = 1; in jpeg_v5_0_0_early_init()
70 adev->jpeg.num_jpeg_rings = 1; in jpeg_v5_0_0_early_init()
93 VCN_5_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); in jpeg_v5_0_0_sw_init()
105 ring = adev->jpeg.inst->ring_dec; in jpeg_v5_0_0_sw_init()
111 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, in jpeg_v5_0_0_sw_init()
116 adev->jpeg.internal.jpeg_pitch[0] = regUVD_JPEG_PITCH_INTERNAL_OFFSET; in jpeg_v5_0_0_sw_init()
117 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH); in jpeg_v5_0_0_sw_init()
123 adev->jpeg.supported_reset = in jpeg_v5_0_0_sw_init()
124 amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]); in jpeg_v5_0_0_sw_init()
126 adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in jpeg_v5_0_0_sw_init()
163 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; in jpeg_v5_0_0_hw_init()
191 cancel_delayed_work_sync(&adev->jpeg.idle_work); in jpeg_v5_0_0_hw_fini()
193 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && in jpeg_v5_0_0_hw_fini()
343 struct amdgpu_ring *ring = adev->jpeg.inst[inst_idx].ring_dec; in jpeg_v5_0_0_start_dpg_mode()
354 adev->jpeg.inst[inst_idx].dpg_sram_curr_addr = in jpeg_v5_0_0_start_dpg_mode()
355 (uint32_t *)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr; in jpeg_v5_0_0_start_dpg_mode()
427 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; in jpeg_v5_0_0_start()
434 r = jpeg_v5_0_0_start_dpg_mode(adev, 0, adev->jpeg.indirect_sram); in jpeg_v5_0_0_start()
606 if (state == adev->jpeg.cur_state) in jpeg_v5_0_0_set_powergating_state()
615 adev->jpeg.cur_state = state; in jpeg_v5_0_0_set_powergating_state()
636 amdgpu_fence_process(adev->jpeg.inst->ring_dec); in jpeg_v5_0_0_process_interrupt()
713 adev->jpeg.inst->ring_dec->funcs = &jpeg_v5_0_0_dec_ring_vm_funcs; in jpeg_v5_0_0_set_dec_ring_funcs()
723 adev->jpeg.inst->irq.num_types = 1; in jpeg_v5_0_0_set_irq_funcs()
724 adev->jpeg.inst->irq.funcs = &jpeg_v5_0_0_irq_funcs; in jpeg_v5_0_0_set_irq_funcs()