Lines Matching refs:mes
145 static int mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, in mes_v12_0_submit_pkt_and_poll_completion() argument
151 struct amdgpu_device *adev = mes->adev; in mes_v12_0_submit_pkt_and_poll_completion()
152 struct amdgpu_ring *ring = &mes->ring[pipe]; in mes_v12_0_submit_pkt_and_poll_completion()
153 spinlock_t *ring_lock = &mes->ring_lock[pipe]; in mes_v12_0_submit_pkt_and_poll_completion()
294 static int mes_v12_0_add_hw_queue(struct amdgpu_mes *mes, in mes_v12_0_add_hw_queue() argument
297 struct amdgpu_device *adev = mes->adev; in mes_v12_0_add_hw_queue()
345 return mes_v12_0_submit_pkt_and_poll_completion(mes, in mes_v12_0_add_hw_queue()
351 static int mes_v12_0_remove_hw_queue(struct amdgpu_mes *mes, in mes_v12_0_remove_hw_queue() argument
365 return mes_v12_0_submit_pkt_and_poll_completion(mes, in mes_v12_0_remove_hw_queue()
403 static int mes_v12_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type, in mes_v12_0_reset_queue_mmio() argument
407 struct amdgpu_device *adev = mes->adev; in mes_v12_0_reset_queue_mmio()
497 static int mes_v12_0_map_legacy_queue(struct amdgpu_mes *mes, in mes_v12_0_map_legacy_queue() argument
518 if (mes->adev->enable_uni_mes) in mes_v12_0_map_legacy_queue()
523 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, in mes_v12_0_map_legacy_queue()
528 static int mes_v12_0_unmap_legacy_queue(struct amdgpu_mes *mes, in mes_v12_0_unmap_legacy_queue() argument
557 if (mes->adev->enable_uni_mes) in mes_v12_0_unmap_legacy_queue()
562 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, in mes_v12_0_unmap_legacy_queue()
567 static int mes_v12_0_suspend_gang(struct amdgpu_mes *mes, in mes_v12_0_suspend_gang() argument
573 static int mes_v12_0_resume_gang(struct amdgpu_mes *mes, in mes_v12_0_resume_gang() argument
579 static int mes_v12_0_query_sched_status(struct amdgpu_mes *mes, int pipe) in mes_v12_0_query_sched_status() argument
589 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, in mes_v12_0_query_sched_status()
594 static int mes_v12_0_misc_op(struct amdgpu_mes *mes, in mes_v12_0_misc_op() argument
600 if (mes->adev->enable_uni_mes) in mes_v12_0_misc_op()
665 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, in mes_v12_0_misc_op()
670 static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes, int pipe) in mes_v12_0_set_hw_resources_1() argument
681 mes->resource_1_gpu_addr[pipe]; in mes_v12_0_set_hw_resources_1()
683 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, in mes_v12_0_set_hw_resources_1()
688 static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe) in mes_v12_0_set_hw_resources() argument
691 struct amdgpu_device *adev = mes->adev; in mes_v12_0_set_hw_resources()
701 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; in mes_v12_0_set_hw_resources()
702 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; in mes_v12_0_set_hw_resources()
708 mes->compute_hqd_mask[i]; in mes_v12_0_set_hw_resources()
712 mes->gfx_hqd_mask[i]; in mes_v12_0_set_hw_resources()
716 mes->sdma_hqd_mask[i]; in mes_v12_0_set_hw_resources()
720 mes->aggregated_doorbells[i]; in mes_v12_0_set_hw_resources()
724 mes->sch_ctx_gpu_addr[pipe]; in mes_v12_0_set_hw_resources()
726 mes->query_status_fence_gpu_addr[pipe]; in mes_v12_0_set_hw_resources()
752 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr + in mes_v12_0_set_hw_resources()
759 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, in mes_v12_0_set_hw_resources()
764 static void mes_v12_0_init_aggregated_doorbell(struct amdgpu_mes *mes) in mes_v12_0_init_aggregated_doorbell() argument
766 struct amdgpu_device *adev = mes->adev; in mes_v12_0_init_aggregated_doorbell()
773 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << in mes_v12_0_init_aggregated_doorbell()
782 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << in mes_v12_0_init_aggregated_doorbell()
791 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << in mes_v12_0_init_aggregated_doorbell()
800 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << in mes_v12_0_init_aggregated_doorbell()
809 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << in mes_v12_0_init_aggregated_doorbell()
820 struct amdgpu_mes *mes, bool enable) in mes_v12_0_enable_unmapped_doorbell_handling() argument
822 struct amdgpu_device *adev = mes->adev; in mes_v12_0_enable_unmapped_doorbell_handling()
839 static int mes_v12_0_reset_hw_queue(struct amdgpu_mes *mes, in mes_v12_0_reset_hw_queue() argument
846 return mes_v12_0_reset_queue_mmio(mes, input->queue_type, in mes_v12_0_reset_hw_queue()
877 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, in mes_v12_0_reset_hw_queue()
902 adev->mes.fw[pipe]->data; in mes_v12_0_allocate_ucode_buffer()
904 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + in mes_v12_0_allocate_ucode_buffer()
911 &adev->mes.ucode_fw_obj[pipe], in mes_v12_0_allocate_ucode_buffer()
912 &adev->mes.ucode_fw_gpu_addr[pipe], in mes_v12_0_allocate_ucode_buffer()
913 (void **)&adev->mes.ucode_fw_ptr[pipe]); in mes_v12_0_allocate_ucode_buffer()
919 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); in mes_v12_0_allocate_ucode_buffer()
921 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); in mes_v12_0_allocate_ucode_buffer()
922 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); in mes_v12_0_allocate_ucode_buffer()
936 adev->mes.fw[pipe]->data; in mes_v12_0_allocate_ucode_data_buffer()
938 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + in mes_v12_0_allocate_ucode_data_buffer()
945 &adev->mes.data_fw_obj[pipe], in mes_v12_0_allocate_ucode_data_buffer()
946 &adev->mes.data_fw_gpu_addr[pipe], in mes_v12_0_allocate_ucode_data_buffer()
947 (void **)&adev->mes.data_fw_ptr[pipe]); in mes_v12_0_allocate_ucode_data_buffer()
953 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); in mes_v12_0_allocate_ucode_data_buffer()
955 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); in mes_v12_0_allocate_ucode_data_buffer()
956 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); in mes_v12_0_allocate_ucode_data_buffer()
964 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], in mes_v12_0_free_ucode_buffers()
965 &adev->mes.data_fw_gpu_addr[pipe], in mes_v12_0_free_ucode_buffers()
966 (void **)&adev->mes.data_fw_ptr[pipe]); in mes_v12_0_free_ucode_buffers()
968 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], in mes_v12_0_free_ucode_buffers()
969 &adev->mes.ucode_fw_gpu_addr[pipe], in mes_v12_0_free_ucode_buffers()
970 (void **)&adev->mes.ucode_fw_ptr[pipe]); in mes_v12_0_free_ucode_buffers()
985 if (adev->mes.event_log_size >= (pipe + 1) * log_size) { in mes_v12_0_enable()
987 lower_32_bits(adev->mes.event_log_gpu_addr + in mes_v12_0_enable()
990 upper_32_bits(adev->mes.event_log_gpu_addr + in mes_v12_0_enable()
1005 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; in mes_v12_0_enable()
1055 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; in mes_v12_0_set_ucode_start_addr()
1075 if (!adev->mes.fw[pipe]) in mes_v12_0_load_microcode()
1096 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); in mes_v12_0_load_microcode()
1098 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); in mes_v12_0_load_microcode()
1105 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); in mes_v12_0_load_microcode()
1107 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); in mes_v12_0_load_microcode()
1139 &adev->mes.eop_gpu_obj[pipe], in mes_v12_0_allocate_eop_buf()
1140 &adev->mes.eop_gpu_addr[pipe], in mes_v12_0_allocate_eop_buf()
1148 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); in mes_v12_0_allocate_eop_buf()
1150 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); in mes_v12_0_allocate_eop_buf()
1151 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); in mes_v12_0_allocate_eop_buf()
1342 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); in mes_v12_0_kiq_enable_queue()
1361 ring = &adev->mes.ring[pipe]; in mes_v12_0_queue_init()
1385 if (((pipe == AMDGPU_MES_SCHED_PIPE) && !adev->mes.sched_version) || in mes_v12_0_queue_init()
1386 ((pipe == AMDGPU_MES_KIQ_PIPE) && !adev->mes.kiq_version)) { in mes_v12_0_queue_init()
1392 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); in mes_v12_0_queue_init()
1394 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); in mes_v12_0_queue_init()
1407 ring = &adev->mes.ring[pipe]; in mes_v12_0_ring_init()
1417 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[pipe]; in mes_v12_0_ring_init()
1446 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; in mes_v12_0_kiq_ring_init()
1464 ring = &adev->mes.ring[pipe]; in mes_v12_0_mqd_sw_init()
1480 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); in mes_v12_0_mqd_sw_init()
1481 if (!adev->mes.mqd_backup[pipe]) in mes_v12_0_mqd_sw_init()
1494 adev->mes.funcs = &mes_v12_0_funcs; in mes_v12_0_sw_init()
1495 adev->mes.kiq_hw_init = &mes_v12_0_kiq_hw_init; in mes_v12_0_sw_init()
1496 adev->mes.kiq_hw_fini = &mes_v12_0_kiq_hw_fini; in mes_v12_0_sw_init()
1497 adev->mes.enable_legacy_queue_map = true; in mes_v12_0_sw_init()
1499 adev->mes.event_log_size = adev->enable_uni_mes ? in mes_v12_0_sw_init()
1524 &adev->mes.resource_1[pipe], in mes_v12_0_sw_init()
1525 &adev->mes.resource_1_gpu_addr[pipe], in mes_v12_0_sw_init()
1526 &adev->mes.resource_1_addr[pipe]); in mes_v12_0_sw_init()
1543 amdgpu_bo_free_kernel(&adev->mes.resource_1[pipe], in mes_v12_0_sw_fini()
1544 &adev->mes.resource_1_gpu_addr[pipe], in mes_v12_0_sw_fini()
1545 &adev->mes.resource_1_addr[pipe]); in mes_v12_0_sw_fini()
1547 kfree(adev->mes.mqd_backup[pipe]); in mes_v12_0_sw_fini()
1549 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], in mes_v12_0_sw_fini()
1550 &adev->mes.eop_gpu_addr[pipe], in mes_v12_0_sw_fini()
1552 amdgpu_ucode_release(&adev->mes.fw[pipe]); in mes_v12_0_sw_fini()
1555 amdgpu_bo_free_kernel(&adev->mes.ring[pipe].mqd_obj, in mes_v12_0_sw_fini()
1556 &adev->mes.ring[pipe].mqd_gpu_addr, in mes_v12_0_sw_fini()
1557 &adev->mes.ring[pipe].mqd_ptr); in mes_v12_0_sw_fini()
1558 amdgpu_ring_fini(&adev->mes.ring[pipe]); in mes_v12_0_sw_fini()
1611 adev->mes.ring[0].sched.ready = false; in mes_v12_0_kiq_dequeue_sched()
1632 mes_v12_0_kiq_setting(&adev->mes.ring[AMDGPU_MES_KIQ_PIPE]); in mes_v12_0_kiq_hw_init()
1668 r = mes_v12_0_set_hw_resources(&adev->mes, AMDGPU_MES_KIQ_PIPE); in mes_v12_0_kiq_hw_init()
1672 mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_KIQ_PIPE); in mes_v12_0_kiq_hw_init()
1675 if (adev->mes.enable_legacy_queue_map) { in mes_v12_0_kiq_hw_init()
1690 if (adev->mes.ring[0].sched.ready) { in mes_v12_0_kiq_hw_fini()
1693 &adev->mes.ring[AMDGPU_MES_SCHED_PIPE], in mes_v12_0_kiq_hw_fini()
1698 adev->mes.ring[0].sched.ready = false; in mes_v12_0_kiq_hw_fini()
1711 if (adev->mes.ring[0].sched.ready) in mes_v12_0_hw_init()
1735 mes_v12_0_enable_unmapped_doorbell_handling(&adev->mes, true); in mes_v12_0_hw_init()
1741 r = mes_v12_0_set_hw_resources(&adev->mes, AMDGPU_MES_SCHED_PIPE); in mes_v12_0_hw_init()
1745 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x4b) in mes_v12_0_hw_init()
1746 mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_SCHED_PIPE); in mes_v12_0_hw_init()
1748 mes_v12_0_init_aggregated_doorbell(&adev->mes); in mes_v12_0_hw_init()
1750 r = mes_v12_0_query_sched_status(&adev->mes, AMDGPU_MES_SCHED_PIPE); in mes_v12_0_hw_init()
1767 adev->mes.ring[0].sched.ready = true; in mes_v12_0_hw_init()