Lines Matching refs:mqd
1158 struct v12_compute_mqd *mqd = ring->mqd_ptr; in mes_v12_0_mqd_init() local
1162 mqd->header = 0xC0310800; in mes_v12_0_mqd_init()
1163 mqd->compute_pipelinestat_enable = 0x00000001; in mes_v12_0_mqd_init()
1164 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; in mes_v12_0_mqd_init()
1165 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; in mes_v12_0_mqd_init()
1166 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; in mes_v12_0_mqd_init()
1167 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; in mes_v12_0_mqd_init()
1168 mqd->compute_misc_reserved = 0x00000007; in mes_v12_0_mqd_init()
1177 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); in mes_v12_0_mqd_init()
1178 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); in mes_v12_0_mqd_init()
1179 mqd->cp_hqd_eop_control = tmp; in mes_v12_0_mqd_init()
1183 mqd->cp_hqd_pq_rptr = 0; in mes_v12_0_mqd_init()
1184 mqd->cp_hqd_pq_wptr_lo = 0; in mes_v12_0_mqd_init()
1185 mqd->cp_hqd_pq_wptr_hi = 0; in mes_v12_0_mqd_init()
1188 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; in mes_v12_0_mqd_init()
1189 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); in mes_v12_0_mqd_init()
1194 mqd->cp_mqd_control = tmp; in mes_v12_0_mqd_init()
1198 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); in mes_v12_0_mqd_init()
1199 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in mes_v12_0_mqd_init()
1203 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; in mes_v12_0_mqd_init()
1204 mqd->cp_hqd_pq_rptr_report_addr_hi = in mes_v12_0_mqd_init()
1209 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; in mes_v12_0_mqd_init()
1210 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in mes_v12_0_mqd_init()
1223 mqd->cp_hqd_pq_control = tmp; in mes_v12_0_mqd_init()
1240 mqd->cp_hqd_pq_doorbell_control = tmp; in mes_v12_0_mqd_init()
1242 mqd->cp_hqd_vmid = 0; in mes_v12_0_mqd_init()
1244 mqd->cp_hqd_active = 1; in mes_v12_0_mqd_init()
1249 mqd->cp_hqd_persistent_state = tmp; in mes_v12_0_mqd_init()
1251 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; in mes_v12_0_mqd_init()
1252 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; in mes_v12_0_mqd_init()
1253 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; in mes_v12_0_mqd_init()
1260 mqd->reserved_184 = BIT(15); in mes_v12_0_mqd_init()
1267 struct v12_compute_mqd *mqd = ring->mqd_ptr; in mes_v12_0_queue_init_register() local
1286 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); in mes_v12_0_queue_init_register()
1287 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); in mes_v12_0_queue_init_register()
1295 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); in mes_v12_0_queue_init_register()
1296 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); in mes_v12_0_queue_init_register()
1300 mqd->cp_hqd_pq_rptr_report_addr_lo); in mes_v12_0_queue_init_register()
1302 mqd->cp_hqd_pq_rptr_report_addr_hi); in mes_v12_0_queue_init_register()
1305 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); in mes_v12_0_queue_init_register()
1309 mqd->cp_hqd_pq_wptr_poll_addr_lo); in mes_v12_0_queue_init_register()
1311 mqd->cp_hqd_pq_wptr_poll_addr_hi); in mes_v12_0_queue_init_register()
1315 mqd->cp_hqd_pq_doorbell_control); in mes_v12_0_queue_init_register()
1318 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); in mes_v12_0_queue_init_register()
1321 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); in mes_v12_0_queue_init_register()