Lines Matching refs:reg_data
496 uint32_t reg_data = 0; in nbio_v2_3_apply_lc_spc_mode_wa() local
503 reg_data = RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL); in nbio_v2_3_apply_lc_spc_mode_wa()
504 link_width = (reg_data & PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) in nbio_v2_3_apply_lc_spc_mode_wa()
512 reg_data = RREG32_PCIE(smnPCIE_LC_CNTL6); in nbio_v2_3_apply_lc_spc_mode_wa()
513 reg_data &= ~PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK; in nbio_v2_3_apply_lc_spc_mode_wa()
514 reg_data |= (0x2 << PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT); in nbio_v2_3_apply_lc_spc_mode_wa()
515 WREG32_PCIE(smnPCIE_LC_CNTL6, reg_data); in nbio_v2_3_apply_lc_spc_mode_wa()
521 uint32_t reg_data = 0; in nbio_v2_3_apply_l1_link_width_reconfig_wa() local
526 reg_data = RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL); in nbio_v2_3_apply_l1_link_width_reconfig_wa()
527 reg_data |= PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK; in nbio_v2_3_apply_l1_link_width_reconfig_wa()
528 WREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL, reg_data); in nbio_v2_3_apply_l1_link_width_reconfig_wa()
533 uint32_t reg, reg_data; in nbio_v2_3_clear_doorbell_interrupt() local
545 reg_data = 1 << BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT; in nbio_v2_3_clear_doorbell_interrupt()
546 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, reg_data); in nbio_v2_3_clear_doorbell_interrupt()