Lines Matching refs:RREG32_SOC15
42 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); in nbio_v7_7_get_rev_id()
61 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE); in nbio_v7_7_get_memsize()
112 reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN); in nbio_v7_7_enable_doorbell_aperture()
148 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, in nbio_v7_7_ih_doorbell_range()
176 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL); in nbio_v7_7_ih_control()
240 def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3); in nbio_v7_7_init_registers()
251 data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4) & ~BIT(23); in nbio_v7_7_init_registers()
265 def = data = RREG32_SOC15(NBIO, 0, regBIF0_CPM_CONTROL); in nbio_v7_7_update_medium_grain_clock_gating()
294 def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_CNTL2); in nbio_v7_7_update_medium_grain_light_sleep()
303 def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_TX_POWER_CTRL_1); in nbio_v7_7_update_medium_grain_light_sleep()
322 data = RREG32_SOC15(NBIO, 0, regBIF0_CPM_CONTROL); in nbio_v7_7_get_clockgating_state()
327 data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_CNTL2); in nbio_v7_7_get_clockgating_state()