Lines Matching refs:adev
210 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, in nv_query_video_codecs() argument
213 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) in nv_query_video_codecs()
216 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { in nv_query_video_codecs()
220 if (amdgpu_sriov_vf(adev)) { in nv_query_video_codecs()
221 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { in nv_query_video_codecs()
233 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { in nv_query_video_codecs()
278 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) in nv_didt_rreg() argument
286 spin_lock_irqsave(&adev->didt_idx_lock, flags); in nv_didt_rreg()
289 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in nv_didt_rreg()
293 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in nv_didt_wreg() argument
300 spin_lock_irqsave(&adev->didt_idx_lock, flags); in nv_didt_wreg()
303 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in nv_didt_wreg()
306 static u32 nv_get_config_memsize(struct amdgpu_device *adev) in nv_get_config_memsize() argument
308 return adev->nbio.funcs->get_memsize(adev); in nv_get_config_memsize()
311 static u32 nv_get_xclk(struct amdgpu_device *adev) in nv_get_xclk() argument
313 return adev->clock.spll.reference_freq; in nv_get_xclk()
317 void nv_grbm_select(struct amdgpu_device *adev, in nv_grbm_select() argument
329 static bool nv_read_disabled_bios(struct amdgpu_device *adev) in nv_read_disabled_bios() argument
357 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in nv_read_indexed_register() argument
362 mutex_lock(&adev->grbm_idx_mutex); in nv_read_indexed_register()
364 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in nv_read_indexed_register()
369 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in nv_read_indexed_register()
370 mutex_unlock(&adev->grbm_idx_mutex); in nv_read_indexed_register()
374 static uint32_t nv_get_register_value(struct amdgpu_device *adev, in nv_get_register_value() argument
379 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); in nv_get_register_value()
382 return adev->gfx.config.gb_addr_config; in nv_get_register_value()
387 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, in nv_read_register() argument
396 if (!adev->reg_offset[en->hwip][en->inst]) in nv_read_register()
398 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in nv_read_register()
402 *value = nv_get_register_value(adev, in nv_read_register()
410 static int nv_asic_mode2_reset(struct amdgpu_device *adev) in nv_asic_mode2_reset() argument
415 amdgpu_atombios_scratch_regs_engine_hung(adev, true); in nv_asic_mode2_reset()
418 pci_clear_master(adev->pdev); in nv_asic_mode2_reset()
420 amdgpu_device_cache_pci_state(adev->pdev); in nv_asic_mode2_reset()
422 ret = amdgpu_dpm_mode2_reset(adev); in nv_asic_mode2_reset()
424 dev_err(adev->dev, "GPU mode2 reset failed\n"); in nv_asic_mode2_reset()
426 amdgpu_device_load_pci_state(adev->pdev); in nv_asic_mode2_reset()
429 for (i = 0; i < adev->usec_timeout; i++) { in nv_asic_mode2_reset()
430 u32 memsize = adev->nbio.funcs->get_memsize(adev); in nv_asic_mode2_reset()
437 amdgpu_atombios_scratch_regs_engine_hung(adev, false); in nv_asic_mode2_reset()
443 nv_asic_reset_method(struct amdgpu_device *adev) in nv_asic_reset_method() argument
452 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", in nv_asic_reset_method()
455 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in nv_asic_reset_method()
469 if (amdgpu_dpm_is_baco_supported(adev)) in nv_asic_reset_method()
476 static int nv_asic_reset(struct amdgpu_device *adev) in nv_asic_reset() argument
480 switch (nv_asic_reset_method(adev)) { in nv_asic_reset()
482 dev_info(adev->dev, "PCI reset\n"); in nv_asic_reset()
483 ret = amdgpu_device_pci_reset(adev); in nv_asic_reset()
486 dev_info(adev->dev, "BACO reset\n"); in nv_asic_reset()
487 ret = amdgpu_dpm_baco_reset(adev); in nv_asic_reset()
490 dev_info(adev->dev, "MODE2 reset\n"); in nv_asic_reset()
491 ret = nv_asic_mode2_reset(adev); in nv_asic_reset()
494 dev_info(adev->dev, "MODE1 reset\n"); in nv_asic_reset()
495 ret = amdgpu_device_mode1_reset(adev); in nv_asic_reset()
502 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in nv_set_uvd_clocks() argument
508 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in nv_set_vce_clocks() argument
514 static void nv_program_aspm(struct amdgpu_device *adev) in nv_program_aspm() argument
516 if (!amdgpu_device_should_use_aspm(adev)) in nv_program_aspm()
519 if (adev->nbio.funcs->program_aspm) in nv_program_aspm()
520 adev->nbio.funcs->program_aspm(adev); in nv_program_aspm()
532 void nv_set_virt_ops(struct amdgpu_device *adev) in nv_set_virt_ops() argument
534 adev->virt.ops = &xgpu_nv_virt_ops; in nv_set_virt_ops()
537 static bool nv_need_full_reset(struct amdgpu_device *adev) in nv_need_full_reset() argument
542 static bool nv_need_reset_on_init(struct amdgpu_device *adev) in nv_need_reset_on_init() argument
546 if (adev->flags & AMD_IS_APU) in nv_need_reset_on_init()
559 static void nv_init_doorbell_index(struct amdgpu_device *adev) in nv_init_doorbell_index() argument
561 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; in nv_init_doorbell_index()
562 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; in nv_init_doorbell_index()
563 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; in nv_init_doorbell_index()
564 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; in nv_init_doorbell_index()
565 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; in nv_init_doorbell_index()
566 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; in nv_init_doorbell_index()
567 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; in nv_init_doorbell_index()
568 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; in nv_init_doorbell_index()
569 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; in nv_init_doorbell_index()
570 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; in nv_init_doorbell_index()
571 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; in nv_init_doorbell_index()
572 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; in nv_init_doorbell_index()
573 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; in nv_init_doorbell_index()
574 adev->doorbell_index.gfx_userqueue_start = in nv_init_doorbell_index()
576 adev->doorbell_index.gfx_userqueue_end = in nv_init_doorbell_index()
578 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; in nv_init_doorbell_index()
579 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; in nv_init_doorbell_index()
580 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; in nv_init_doorbell_index()
581 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; in nv_init_doorbell_index()
582 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; in nv_init_doorbell_index()
583 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; in nv_init_doorbell_index()
584 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; in nv_init_doorbell_index()
585 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; in nv_init_doorbell_index()
586 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; in nv_init_doorbell_index()
587 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; in nv_init_doorbell_index()
588 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; in nv_init_doorbell_index()
589 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; in nv_init_doorbell_index()
590 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; in nv_init_doorbell_index()
592 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; in nv_init_doorbell_index()
593 adev->doorbell_index.sdma_doorbell_range = 20; in nv_init_doorbell_index()
596 static void nv_pre_asic_init(struct amdgpu_device *adev) in nv_pre_asic_init() argument
600 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, in nv_update_umd_stable_pstate() argument
604 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); in nv_update_umd_stable_pstate()
606 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); in nv_update_umd_stable_pstate()
608 if (adev->gfx.funcs->update_perfmon_mgcg) in nv_update_umd_stable_pstate()
609 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); in nv_update_umd_stable_pstate()
611 if (adev->nbio.funcs->enable_aspm && in nv_update_umd_stable_pstate()
612 amdgpu_device_should_use_aspm(adev)) in nv_update_umd_stable_pstate()
613 adev->nbio.funcs->enable_aspm(adev, !enter); in nv_update_umd_stable_pstate()
640 struct amdgpu_device *adev = ip_block->adev; in nv_common_early_init() local
642 adev->nbio.funcs->set_reg_remap(adev); in nv_common_early_init()
643 adev->smc_rreg = NULL; in nv_common_early_init()
644 adev->smc_wreg = NULL; in nv_common_early_init()
645 adev->pcie_rreg = &amdgpu_device_indirect_rreg; in nv_common_early_init()
646 adev->pcie_wreg = &amdgpu_device_indirect_wreg; in nv_common_early_init()
647 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; in nv_common_early_init()
648 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; in nv_common_early_init()
649 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; in nv_common_early_init()
650 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; in nv_common_early_init()
653 adev->uvd_ctx_rreg = NULL; in nv_common_early_init()
654 adev->uvd_ctx_wreg = NULL; in nv_common_early_init()
656 adev->didt_rreg = &nv_didt_rreg; in nv_common_early_init()
657 adev->didt_wreg = &nv_didt_wreg; in nv_common_early_init()
659 adev->asic_funcs = &nv_asic_funcs; in nv_common_early_init()
661 adev->rev_id = amdgpu_device_get_rev_id(adev); in nv_common_early_init()
662 adev->external_rev_id = 0xff; in nv_common_early_init()
666 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in nv_common_early_init()
668 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
683 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
687 adev->external_rev_id = adev->rev_id + 0x1; in nv_common_early_init()
690 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
705 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
708 adev->external_rev_id = adev->rev_id + 20; in nv_common_early_init()
711 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
727 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
735 if (amdgpu_sriov_vf(adev)) in nv_common_early_init()
736 adev->rev_id = 0; in nv_common_early_init()
737 adev->external_rev_id = adev->rev_id + 0xa; in nv_common_early_init()
740 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
751 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
756 if (amdgpu_sriov_vf(adev)) { in nv_common_early_init()
758 adev->cg_flags = 0; in nv_common_early_init()
759 adev->pg_flags = 0; in nv_common_early_init()
761 adev->external_rev_id = adev->rev_id + 0x28; in nv_common_early_init()
764 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
775 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
780 adev->external_rev_id = adev->rev_id + 0x32; in nv_common_early_init()
783 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
798 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | in nv_common_early_init()
802 if (adev->apu_flags & AMD_APU_IS_VANGOGH) in nv_common_early_init()
803 adev->external_rev_id = adev->rev_id + 0x01; in nv_common_early_init()
806 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
817 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
822 adev->external_rev_id = adev->rev_id + 0x3c; in nv_common_early_init()
825 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
835 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
839 adev->external_rev_id = adev->rev_id + 0x46; in nv_common_early_init()
842 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
862 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | in nv_common_early_init()
866 if (adev->pdev->device == 0x1681) in nv_common_early_init()
867 adev->external_rev_id = 0x20; in nv_common_early_init()
869 adev->external_rev_id = adev->rev_id + 0x01; in nv_common_early_init()
873 adev->cg_flags = 0; in nv_common_early_init()
874 adev->pg_flags = 0; in nv_common_early_init()
875 adev->external_rev_id = adev->rev_id + 0x82; in nv_common_early_init()
878 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
897 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | in nv_common_early_init()
901 adev->external_rev_id = adev->rev_id + 0x01; in nv_common_early_init()
904 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
924 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
928 adev->external_rev_id = adev->rev_id + 0x01; in nv_common_early_init()
935 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) in nv_common_early_init()
936 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN | in nv_common_early_init()
940 if (amdgpu_sriov_vf(adev)) { in nv_common_early_init()
941 amdgpu_virt_init_setting(adev); in nv_common_early_init()
942 xgpu_nv_mailbox_set_irq_funcs(adev); in nv_common_early_init()
950 struct amdgpu_device *adev = ip_block->adev; in nv_common_late_init() local
952 if (amdgpu_sriov_vf(adev)) { in nv_common_late_init()
953 xgpu_nv_mailbox_get_irq(adev); in nv_common_late_init()
954 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { in nv_common_late_init()
955 amdgpu_virt_update_sriov_video_codec(adev, in nv_common_late_init()
961 amdgpu_virt_update_sriov_video_codec(adev, in nv_common_late_init()
972 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); in nv_common_late_init()
979 struct amdgpu_device *adev = ip_block->adev; in nv_common_sw_init() local
981 if (amdgpu_sriov_vf(adev)) in nv_common_sw_init()
982 xgpu_nv_mailbox_add_irq_id(adev); in nv_common_sw_init()
989 struct amdgpu_device *adev = ip_block->adev; in nv_common_hw_init() local
991 if (adev->nbio.funcs->apply_lc_spc_mode_wa) in nv_common_hw_init()
992 adev->nbio.funcs->apply_lc_spc_mode_wa(adev); in nv_common_hw_init()
994 if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa) in nv_common_hw_init()
995 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev); in nv_common_hw_init()
998 nv_program_aspm(adev); in nv_common_hw_init()
1000 adev->nbio.funcs->init_registers(adev); in nv_common_hw_init()
1005 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) in nv_common_hw_init()
1006 adev->nbio.funcs->remap_hdp_registers(adev); in nv_common_hw_init()
1008 adev->nbio.funcs->enable_doorbell_aperture(adev, true); in nv_common_hw_init()
1015 struct amdgpu_device *adev = ip_block->adev; in nv_common_hw_fini() local
1022 adev->nbio.funcs->enable_doorbell_aperture(adev, false); in nv_common_hw_fini()
1023 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); in nv_common_hw_fini()
1046 struct amdgpu_device *adev = ip_block->adev; in nv_common_set_clockgating_state() local
1048 if (amdgpu_sriov_vf(adev)) in nv_common_set_clockgating_state()
1051 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in nv_common_set_clockgating_state()
1059 adev->nbio.funcs->update_medium_grain_clock_gating(adev, in nv_common_set_clockgating_state()
1061 adev->nbio.funcs->update_medium_grain_light_sleep(adev, in nv_common_set_clockgating_state()
1063 adev->hdp.funcs->update_clock_gating(adev, in nv_common_set_clockgating_state()
1065 adev->smuio.funcs->update_rom_clock_gating(adev, in nv_common_set_clockgating_state()
1083 struct amdgpu_device *adev = ip_block->adev; in nv_common_get_clockgating_state() local
1085 if (amdgpu_sriov_vf(adev)) in nv_common_get_clockgating_state()
1088 adev->nbio.funcs->get_clockgating_state(adev, flags); in nv_common_get_clockgating_state()
1090 adev->hdp.funcs->get_clock_gating_state(adev, flags); in nv_common_get_clockgating_state()
1092 adev->smuio.funcs->get_clock_gating_state(adev, flags); in nv_common_get_clockgating_state()