Lines Matching refs:ib
432 struct amdgpu_ib *ib, in sdma_v5_0_ring_emit_ib() argument
451 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v5_0_ring_emit_ib()
452 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v5_0_ring_emit_ib()
453 amdgpu_ring_write(ring, ib->length_dw); in sdma_v5_0_ring_emit_ib()
1077 struct amdgpu_ib ib; in sdma_v5_0_ring_test_ib() local
1085 memset(&ib, 0, sizeof(ib)); in sdma_v5_0_ring_test_ib()
1097 AMDGPU_IB_POOL_DIRECT, &ib); in sdma_v5_0_ring_test_ib()
1103 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | in sdma_v5_0_ring_test_ib()
1105 ib.ptr[1] = lower_32_bits(gpu_addr); in sdma_v5_0_ring_test_ib()
1106 ib.ptr[2] = upper_32_bits(gpu_addr); in sdma_v5_0_ring_test_ib()
1107 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); in sdma_v5_0_ring_test_ib()
1108 ib.ptr[4] = 0xDEADBEEF; in sdma_v5_0_ring_test_ib()
1109 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); in sdma_v5_0_ring_test_ib()
1110 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); in sdma_v5_0_ring_test_ib()
1111 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); in sdma_v5_0_ring_test_ib()
1112 ib.length_dw = 8; in sdma_v5_0_ring_test_ib()
1114 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); in sdma_v5_0_ring_test_ib()
1136 amdgpu_ib_free(&ib, NULL); in sdma_v5_0_ring_test_ib()
1154 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib, in sdma_v5_0_vm_copy_pte() argument
1160 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | in sdma_v5_0_vm_copy_pte()
1162 ib->ptr[ib->length_dw++] = bytes - 1; in sdma_v5_0_vm_copy_pte()
1163 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ in sdma_v5_0_vm_copy_pte()
1164 ib->ptr[ib->length_dw++] = lower_32_bits(src); in sdma_v5_0_vm_copy_pte()
1165 ib->ptr[ib->length_dw++] = upper_32_bits(src); in sdma_v5_0_vm_copy_pte()
1166 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in sdma_v5_0_vm_copy_pte()
1167 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v5_0_vm_copy_pte()
1182 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, in sdma_v5_0_vm_write_pte() argument
1188 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | in sdma_v5_0_vm_write_pte()
1190 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in sdma_v5_0_vm_write_pte()
1191 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v5_0_vm_write_pte()
1192 ib->ptr[ib->length_dw++] = ndw - 1; in sdma_v5_0_vm_write_pte()
1194 ib->ptr[ib->length_dw++] = lower_32_bits(value); in sdma_v5_0_vm_write_pte()
1195 ib->ptr[ib->length_dw++] = upper_32_bits(value); in sdma_v5_0_vm_write_pte()
1212 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib, in sdma_v5_0_vm_set_pte_pde() argument
1218 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); in sdma_v5_0_vm_set_pte_pde()
1219 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ in sdma_v5_0_vm_set_pte_pde()
1220 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v5_0_vm_set_pte_pde()
1221 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ in sdma_v5_0_vm_set_pte_pde()
1222 ib->ptr[ib->length_dw++] = upper_32_bits(flags); in sdma_v5_0_vm_set_pte_pde()
1223 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ in sdma_v5_0_vm_set_pte_pde()
1224 ib->ptr[ib->length_dw++] = upper_32_bits(addr); in sdma_v5_0_vm_set_pte_pde()
1225 ib->ptr[ib->length_dw++] = incr; /* increment size */ in sdma_v5_0_vm_set_pte_pde()
1226 ib->ptr[ib->length_dw++] = 0; in sdma_v5_0_vm_set_pte_pde()
1227 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ in sdma_v5_0_vm_set_pte_pde()
1237 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) in sdma_v5_0_ring_pad_ib() argument
1243 pad_count = (-ib->length_dw) & 0x7; in sdma_v5_0_ring_pad_ib()
1246 ib->ptr[ib->length_dw++] = in sdma_v5_0_ring_pad_ib()
1250 ib->ptr[ib->length_dw++] = in sdma_v5_0_ring_pad_ib()
2018 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib, in sdma_v5_0_emit_copy_buffer() argument
2024 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | in sdma_v5_0_emit_copy_buffer()
2027 ib->ptr[ib->length_dw++] = byte_count - 1; in sdma_v5_0_emit_copy_buffer()
2028 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ in sdma_v5_0_emit_copy_buffer()
2029 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); in sdma_v5_0_emit_copy_buffer()
2030 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); in sdma_v5_0_emit_copy_buffer()
2031 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); in sdma_v5_0_emit_copy_buffer()
2032 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); in sdma_v5_0_emit_copy_buffer()
2045 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib, in sdma_v5_0_emit_fill_buffer() argument
2050 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); in sdma_v5_0_emit_fill_buffer()
2051 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); in sdma_v5_0_emit_fill_buffer()
2052 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); in sdma_v5_0_emit_fill_buffer()
2053 ib->ptr[ib->length_dw++] = src_data; in sdma_v5_0_emit_fill_buffer()
2054 ib->ptr[ib->length_dw++] = byte_count - 1; in sdma_v5_0_emit_fill_buffer()