Lines Matching refs:sdma
294 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_init_microcode()
409 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v5_0_ring_insert_nop() local
413 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v5_0_ring_insert_nop()
627 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_ctx_switch_enable()
662 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); in sdma_v5_0_enable()
671 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_enable()
699 ring = &adev->sdma.instance[i].ring; in sdma_v5_0_gfx_resume_instance()
853 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_gfx_resume()
893 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_load_microcode()
894 if (!adev->sdma.instance[i].fw) in sdma_v5_0_load_microcode()
897 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; in sdma_v5_0_load_microcode()
902 (adev->sdma.instance[i].fw->data + in sdma_v5_0_load_microcode()
913 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); in sdma_v5_0_load_microcode()
1239 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v5_0_ring_pad_ib() local
1245 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v5_0_ring_pad_ib()
1390 &adev->sdma.trap_irq); in sdma_v5_0_sw_init()
1397 &adev->sdma.trap_irq); in sdma_v5_0_sw_init()
1401 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_sw_init()
1402 mutex_init(&adev->sdma.instance[i].engine_reset_mutex); in sdma_v5_0_sw_init()
1403 adev->sdma.instance[i].funcs = &sdma_v5_0_sdma_funcs; in sdma_v5_0_sw_init()
1404 ring = &adev->sdma.instance[i].ring; in sdma_v5_0_sw_init()
1417 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, in sdma_v5_0_sw_init()
1425 adev->sdma.supported_reset = in sdma_v5_0_sw_init()
1426 amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); in sdma_v5_0_sw_init()
1431 if ((adev->sdma.instance[0].fw_version >= 35) && in sdma_v5_0_sw_init()
1433 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in sdma_v5_0_sw_init()
1440 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL); in sdma_v5_0_sw_init()
1442 adev->sdma.ip_dump = ptr; in sdma_v5_0_sw_init()
1458 for (i = 0; i < adev->sdma.num_instances; i++) in sdma_v5_0_sw_fini()
1459 amdgpu_ring_fini(&adev->sdma.instance[i].ring); in sdma_v5_0_sw_fini()
1464 kfree(adev->sdma.ip_dump); in sdma_v5_0_sw_fini()
1509 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_is_idle()
1550 if (ring->me >= adev->sdma.num_instances) { in sdma_v5_0_reset_queue()
1729 amdgpu_fence_process(&adev->sdma.instance[0].ring); in sdma_v5_0_process_trap_irq()
1745 amdgpu_fence_process(&adev->sdma.instance[1].ring); in sdma_v5_0_process_trap_irq()
1775 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_update_medium_grain_clock_gating()
1812 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_update_medium_grain_light_sleep()
1887 if (!adev->sdma.ip_dump) in sdma_v5_0_print_ip_state()
1890 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances); in sdma_v5_0_print_ip_state()
1891 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_print_ip_state()
1897 adev->sdma.ip_dump[instance_offset + j]); in sdma_v5_0_print_ip_state()
1908 if (!adev->sdma.ip_dump) in sdma_v5_0_dump_ip_state()
1912 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_dump_ip_state()
1915 adev->sdma.ip_dump[instance_offset + j] = in sdma_v5_0_dump_ip_state()
1982 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_set_ring_funcs()
1983 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs; in sdma_v5_0_set_ring_funcs()
1984 adev->sdma.instance[i].ring.me = i; in sdma_v5_0_set_ring_funcs()
1999 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + in sdma_v5_0_set_irq_funcs()
2000 adev->sdma.num_instances; in sdma_v5_0_set_irq_funcs()
2001 adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs; in sdma_v5_0_set_irq_funcs()
2002 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs; in sdma_v5_0_set_irq_funcs()
2071 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; in sdma_v5_0_set_buffer_funcs()
2088 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_set_vm_pte_funcs()
2090 &adev->sdma.instance[i].ring.sched; in sdma_v5_0_set_vm_pte_funcs()
2092 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in sdma_v5_0_set_vm_pte_funcs()