Lines Matching refs:ib
280 struct amdgpu_ib *ib, in sdma_v5_2_ring_emit_ib() argument
299 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v5_2_ring_emit_ib()
300 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v5_2_ring_emit_ib()
301 amdgpu_ring_write(ring, ib->length_dw); in sdma_v5_2_ring_emit_ib()
977 struct amdgpu_ib ib; in sdma_v5_2_ring_test_ib() local
985 memset(&ib, 0, sizeof(ib)); in sdma_v5_2_ring_test_ib()
996 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); in sdma_v5_2_ring_test_ib()
1002 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | in sdma_v5_2_ring_test_ib()
1004 ib.ptr[1] = lower_32_bits(gpu_addr); in sdma_v5_2_ring_test_ib()
1005 ib.ptr[2] = upper_32_bits(gpu_addr); in sdma_v5_2_ring_test_ib()
1006 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); in sdma_v5_2_ring_test_ib()
1007 ib.ptr[4] = 0xDEADBEEF; in sdma_v5_2_ring_test_ib()
1008 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); in sdma_v5_2_ring_test_ib()
1009 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); in sdma_v5_2_ring_test_ib()
1010 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); in sdma_v5_2_ring_test_ib()
1011 ib.length_dw = 8; in sdma_v5_2_ring_test_ib()
1013 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); in sdma_v5_2_ring_test_ib()
1035 amdgpu_ib_free(&ib, NULL); in sdma_v5_2_ring_test_ib()
1053 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib, in sdma_v5_2_vm_copy_pte() argument
1059 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | in sdma_v5_2_vm_copy_pte()
1061 ib->ptr[ib->length_dw++] = bytes - 1; in sdma_v5_2_vm_copy_pte()
1062 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ in sdma_v5_2_vm_copy_pte()
1063 ib->ptr[ib->length_dw++] = lower_32_bits(src); in sdma_v5_2_vm_copy_pte()
1064 ib->ptr[ib->length_dw++] = upper_32_bits(src); in sdma_v5_2_vm_copy_pte()
1065 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in sdma_v5_2_vm_copy_pte()
1066 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v5_2_vm_copy_pte()
1081 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, in sdma_v5_2_vm_write_pte() argument
1087 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | in sdma_v5_2_vm_write_pte()
1089 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in sdma_v5_2_vm_write_pte()
1090 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v5_2_vm_write_pte()
1091 ib->ptr[ib->length_dw++] = ndw - 1; in sdma_v5_2_vm_write_pte()
1093 ib->ptr[ib->length_dw++] = lower_32_bits(value); in sdma_v5_2_vm_write_pte()
1094 ib->ptr[ib->length_dw++] = upper_32_bits(value); in sdma_v5_2_vm_write_pte()
1111 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib, in sdma_v5_2_vm_set_pte_pde() argument
1117 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); in sdma_v5_2_vm_set_pte_pde()
1118 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ in sdma_v5_2_vm_set_pte_pde()
1119 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v5_2_vm_set_pte_pde()
1120 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ in sdma_v5_2_vm_set_pte_pde()
1121 ib->ptr[ib->length_dw++] = upper_32_bits(flags); in sdma_v5_2_vm_set_pte_pde()
1122 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ in sdma_v5_2_vm_set_pte_pde()
1123 ib->ptr[ib->length_dw++] = upper_32_bits(addr); in sdma_v5_2_vm_set_pte_pde()
1124 ib->ptr[ib->length_dw++] = incr; /* increment size */ in sdma_v5_2_vm_set_pte_pde()
1125 ib->ptr[ib->length_dw++] = 0; in sdma_v5_2_vm_set_pte_pde()
1126 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ in sdma_v5_2_vm_set_pte_pde()
1137 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) in sdma_v5_2_ring_pad_ib() argument
1143 pad_count = (-ib->length_dw) & 0x7; in sdma_v5_2_ring_pad_ib()
1146 ib->ptr[ib->length_dw++] = in sdma_v5_2_ring_pad_ib()
1150 ib->ptr[ib->length_dw++] = in sdma_v5_2_ring_pad_ib()
2028 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib, in sdma_v5_2_emit_copy_buffer() argument
2034 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | in sdma_v5_2_emit_copy_buffer()
2037 ib->ptr[ib->length_dw++] = byte_count - 1; in sdma_v5_2_emit_copy_buffer()
2038 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ in sdma_v5_2_emit_copy_buffer()
2039 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); in sdma_v5_2_emit_copy_buffer()
2040 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); in sdma_v5_2_emit_copy_buffer()
2041 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); in sdma_v5_2_emit_copy_buffer()
2042 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); in sdma_v5_2_emit_copy_buffer()
2055 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib, in sdma_v5_2_emit_fill_buffer() argument
2060 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); in sdma_v5_2_emit_fill_buffer()
2061 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); in sdma_v5_2_emit_fill_buffer()
2062 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); in sdma_v5_2_emit_fill_buffer()
2063 ib->ptr[ib->length_dw++] = src_data; in sdma_v5_2_emit_fill_buffer()
2064 ib->ptr[ib->length_dw++] = byte_count - 1; in sdma_v5_2_emit_fill_buffer()