Lines Matching refs:sdma
257 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v5_2_ring_insert_nop() local
261 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v5_2_ring_insert_nop()
477 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_ctx_switch_enable()
511 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); in sdma_v5_2_enable()
518 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_enable()
548 ring = &adev->sdma.instance[i].ring; in sdma_v5_2_gfx_resume_instance()
700 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_gfx_resume()
740 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_load_microcode()
741 if (!adev->sdma.instance[i].fw) in sdma_v5_2_load_microcode()
744 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; in sdma_v5_2_load_microcode()
749 (adev->sdma.instance[i].fw->data + in sdma_v5_2_load_microcode()
760 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); in sdma_v5_2_load_microcode()
795 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_soft_reset()
1139 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v5_2_ring_pad_ib() local
1145 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v5_2_ring_pad_ib()
1312 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_sw_init()
1315 &adev->sdma.trap_irq); in sdma_v5_2_sw_init()
1320 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_sw_init()
1321 mutex_init(&adev->sdma.instance[i].engine_reset_mutex); in sdma_v5_2_sw_init()
1322 adev->sdma.instance[i].funcs = &sdma_v5_2_sdma_funcs; in sdma_v5_2_sw_init()
1323 ring = &adev->sdma.instance[i].ring; in sdma_v5_2_sw_init()
1336 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, in sdma_v5_2_sw_init()
1343 adev->sdma.supported_reset = in sdma_v5_2_sw_init()
1344 amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); in sdma_v5_2_sw_init()
1350 if ((adev->sdma.instance[0].fw_version >= 76) && in sdma_v5_2_sw_init()
1352 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in sdma_v5_2_sw_init()
1355 if ((adev->sdma.instance[0].fw_version >= 34) && in sdma_v5_2_sw_init()
1357 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in sdma_v5_2_sw_init()
1364 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL); in sdma_v5_2_sw_init()
1366 adev->sdma.ip_dump = ptr; in sdma_v5_2_sw_init()
1382 for (i = 0; i < adev->sdma.num_instances; i++) in sdma_v5_2_sw_fini()
1383 amdgpu_ring_fini(&adev->sdma.instance[i].ring); in sdma_v5_2_sw_fini()
1388 kfree(adev->sdma.ip_dump); in sdma_v5_2_sw_fini()
1428 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_is_idle()
1464 if (ring->me >= adev->sdma.num_instances) { in sdma_v5_2_reset_queue()
1641 amdgpu_fence_process(&adev->sdma.instance[0].ring); in sdma_v5_2_process_trap_irq()
1657 amdgpu_fence_process(&adev->sdma.instance[1].ring); in sdma_v5_2_process_trap_irq()
1673 amdgpu_fence_process(&adev->sdma.instance[2].ring); in sdma_v5_2_process_trap_irq()
1689 amdgpu_fence_process(&adev->sdma.instance[3].ring); in sdma_v5_2_process_trap_irq()
1718 if (adev->sdma.instance[i].fw_version < 70) in sdma_v5_2_firmware_mgcg_support()
1722 if (adev->sdma.instance[i].fw_version < 47) in sdma_v5_2_firmware_mgcg_support()
1726 if (adev->sdma.instance[i].fw_version < 9) in sdma_v5_2_firmware_mgcg_support()
1743 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_update_medium_grain_clock_gating()
1780 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_update_medium_grain_light_sleep()
1781 if (adev->sdma.instance[i].fw_version < 70 && in sdma_v5_2_update_medium_grain_light_sleep()
1895 if (!adev->sdma.ip_dump) in sdma_v5_2_print_ip_state()
1898 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances); in sdma_v5_2_print_ip_state()
1899 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_print_ip_state()
1905 adev->sdma.ip_dump[instance_offset + j]); in sdma_v5_2_print_ip_state()
1916 if (!adev->sdma.ip_dump) in sdma_v5_2_dump_ip_state()
1920 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_dump_ip_state()
1923 adev->sdma.ip_dump[instance_offset + j] = in sdma_v5_2_dump_ip_state()
1992 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_set_ring_funcs()
1993 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs; in sdma_v5_2_set_ring_funcs()
1994 adev->sdma.instance[i].ring.me = i; in sdma_v5_2_set_ring_funcs()
2009 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + in sdma_v5_2_set_irq_funcs()
2010 adev->sdma.num_instances; in sdma_v5_2_set_irq_funcs()
2011 adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs; in sdma_v5_2_set_irq_funcs()
2012 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs; in sdma_v5_2_set_irq_funcs()
2081 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; in sdma_v5_2_set_buffer_funcs()
2098 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_set_vm_pte_funcs()
2100 &adev->sdma.instance[i].ring.sched; in sdma_v5_2_set_vm_pte_funcs()
2102 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in sdma_v5_2_set_vm_pte_funcs()