Lines Matching refs:amdgpu_ring_write
88 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0)); in si_dma_ring_emit_ib()
89 amdgpu_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, vmid, 0)); in si_dma_ring_emit_ib()
90 amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in si_dma_ring_emit_ib()
91 amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in si_dma_ring_emit_ib()
113 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0, 0)); in si_dma_ring_emit_fence()
114 amdgpu_ring_write(ring, addr & 0xfffffffc); in si_dma_ring_emit_fence()
115 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff)); in si_dma_ring_emit_fence()
116 amdgpu_ring_write(ring, seq); in si_dma_ring_emit_fence()
120 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0, 0)); in si_dma_ring_emit_fence()
121 amdgpu_ring_write(ring, addr & 0xfffffffc); in si_dma_ring_emit_fence()
122 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff)); in si_dma_ring_emit_fence()
123 amdgpu_ring_write(ring, upper_32_bits(seq)); in si_dma_ring_emit_fence()
126 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0, 0)); in si_dma_ring_emit_fence()
229 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, 1)); in si_dma_ring_test_ring()
230 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in si_dma_ring_test_ring()
231 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xff); in si_dma_ring_test_ring()
232 amdgpu_ring_write(ring, 0xDEADBEEF); in si_dma_ring_test_ring()
435 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_POLL_REG_MEM, 0, 0, 0, 0) | in si_dma_ring_emit_pipeline_sync()
437 amdgpu_ring_write(ring, lower_32_bits(addr)); in si_dma_ring_emit_pipeline_sync()
438 amdgpu_ring_write(ring, (0xff << 16) | upper_32_bits(addr)); /* retry, addr_hi */ in si_dma_ring_emit_pipeline_sync()
439 amdgpu_ring_write(ring, 0xffffffff); /* mask */ in si_dma_ring_emit_pipeline_sync()
440 amdgpu_ring_write(ring, seq); /* value */ in si_dma_ring_emit_pipeline_sync()
441 amdgpu_ring_write(ring, (3 << 28) | 0x20); /* func(equal) | poll interval */ in si_dma_ring_emit_pipeline_sync()
460 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_POLL_REG_MEM, 0, 0, 0, 0)); in si_dma_ring_emit_vm_flush()
461 amdgpu_ring_write(ring, VM_INVALIDATE_REQUEST); in si_dma_ring_emit_vm_flush()
462 amdgpu_ring_write(ring, 0xff << 16); /* retry */ in si_dma_ring_emit_vm_flush()
463 amdgpu_ring_write(ring, 1 << vmid); /* mask */ in si_dma_ring_emit_vm_flush()
464 amdgpu_ring_write(ring, 0); /* value */ in si_dma_ring_emit_vm_flush()
465 amdgpu_ring_write(ring, (0 << 28) | 0x20); /* func(always) | poll interval */ in si_dma_ring_emit_vm_flush()
471 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); in si_dma_ring_emit_wreg()
472 amdgpu_ring_write(ring, (0xf << 16) | reg); in si_dma_ring_emit_wreg()
473 amdgpu_ring_write(ring, val); in si_dma_ring_emit_wreg()