Lines Matching refs:ib
80 struct amdgpu_ib *ib, in si_dma_ring_emit_ib() argument
90 amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in si_dma_ring_emit_ib()
91 amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in si_dma_ring_emit_ib()
262 struct amdgpu_ib ib; in si_dma_ring_test_ib() local
276 memset(&ib, 0, sizeof(ib)); in si_dma_ring_test_ib()
278 AMDGPU_IB_POOL_DIRECT, &ib); in si_dma_ring_test_ib()
282 ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, 1); in si_dma_ring_test_ib()
283 ib.ptr[1] = lower_32_bits(gpu_addr); in si_dma_ring_test_ib()
284 ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff; in si_dma_ring_test_ib()
285 ib.ptr[3] = 0xDEADBEEF; in si_dma_ring_test_ib()
286 ib.length_dw = 4; in si_dma_ring_test_ib()
287 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); in si_dma_ring_test_ib()
305 amdgpu_ib_free(&ib, NULL); in si_dma_ring_test_ib()
322 static void si_dma_vm_copy_pte(struct amdgpu_ib *ib, in si_dma_vm_copy_pte() argument
328 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY, in si_dma_vm_copy_pte()
330 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in si_dma_vm_copy_pte()
331 ib->ptr[ib->length_dw++] = lower_32_bits(src); in si_dma_vm_copy_pte()
332 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_copy_pte()
333 ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; in si_dma_vm_copy_pte()
347 static void si_dma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, in si_dma_vm_write_pte() argument
353 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw); in si_dma_vm_write_pte()
354 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in si_dma_vm_write_pte()
355 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in si_dma_vm_write_pte()
357 ib->ptr[ib->length_dw++] = lower_32_bits(value); in si_dma_vm_write_pte()
358 ib->ptr[ib->length_dw++] = upper_32_bits(value); in si_dma_vm_write_pte()
375 static void si_dma_vm_set_pte_pde(struct amdgpu_ib *ib, in si_dma_vm_set_pte_pde() argument
394 ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw); in si_dma_vm_set_pte_pde()
395 ib->ptr[ib->length_dw++] = pe; /* dst addr */ in si_dma_vm_set_pte_pde()
396 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_set_pte_pde()
397 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ in si_dma_vm_set_pte_pde()
398 ib->ptr[ib->length_dw++] = upper_32_bits(flags); in si_dma_vm_set_pte_pde()
399 ib->ptr[ib->length_dw++] = value; /* value */ in si_dma_vm_set_pte_pde()
400 ib->ptr[ib->length_dw++] = upper_32_bits(value); in si_dma_vm_set_pte_pde()
401 ib->ptr[ib->length_dw++] = incr; /* increment size */ in si_dma_vm_set_pte_pde()
402 ib->ptr[ib->length_dw++] = 0; in si_dma_vm_set_pte_pde()
416 static void si_dma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) in si_dma_ring_pad_ib() argument
418 while (ib->length_dw & 0x7) in si_dma_ring_pad_ib()
419 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0); in si_dma_ring_pad_ib()
780 static void si_dma_emit_copy_buffer(struct amdgpu_ib *ib, in si_dma_emit_copy_buffer() argument
786 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY, in si_dma_emit_copy_buffer()
788 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); in si_dma_emit_copy_buffer()
789 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); in si_dma_emit_copy_buffer()
790 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset) & 0xff; in si_dma_emit_copy_buffer()
791 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset) & 0xff; in si_dma_emit_copy_buffer()
804 static void si_dma_emit_fill_buffer(struct amdgpu_ib *ib, in si_dma_emit_fill_buffer() argument
809 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_CONSTANT_FILL, in si_dma_emit_fill_buffer()
811 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); in si_dma_emit_fill_buffer()
812 ib->ptr[ib->length_dw++] = src_data; in si_dma_emit_fill_buffer()
813 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset) << 16; in si_dma_emit_fill_buffer()