Lines Matching refs:adev
190 static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode, in soc15_query_video_codecs() argument
193 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) { in soc15_query_video_codecs()
194 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) { in soc15_query_video_codecs()
206 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { in soc15_query_video_codecs()
240 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) in soc15_uvd_ctx_rreg() argument
248 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_rreg()
251 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_rreg()
255 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_uvd_ctx_wreg() argument
262 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_wreg()
265 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_wreg()
268 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) in soc15_didt_rreg() argument
276 spin_lock_irqsave(&adev->didt_idx_lock, flags); in soc15_didt_rreg()
279 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in soc15_didt_rreg()
283 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_didt_wreg() argument
290 spin_lock_irqsave(&adev->didt_idx_lock, flags); in soc15_didt_wreg()
293 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in soc15_didt_wreg()
296 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) in soc15_gc_cac_rreg() argument
301 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_rreg()
304 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_rreg()
308 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_gc_cac_wreg() argument
312 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_wreg()
315 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_wreg()
318 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) in soc15_se_cac_rreg() argument
323 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); in soc15_se_cac_rreg()
326 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); in soc15_se_cac_rreg()
330 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_se_cac_wreg() argument
334 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); in soc15_se_cac_wreg()
337 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); in soc15_se_cac_wreg()
340 static u32 soc15_get_config_memsize(struct amdgpu_device *adev) in soc15_get_config_memsize() argument
342 return adev->nbio.funcs->get_memsize(adev); in soc15_get_config_memsize()
345 static u32 soc15_get_xclk(struct amdgpu_device *adev) in soc15_get_xclk() argument
347 u32 reference_clock = adev->clock.spll.reference_freq; in soc15_get_xclk()
349 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 0) || in soc15_get_xclk()
350 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 1) || in soc15_get_xclk()
351 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 6) || in soc15_get_xclk()
352 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) || in soc15_get_xclk()
353 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 14)) in soc15_get_xclk()
355 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 0) || in soc15_get_xclk()
356 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 1)) in soc15_get_xclk()
363 void soc15_grbm_select(struct amdgpu_device *adev, in soc15_grbm_select() argument
375 static bool soc15_read_disabled_bios(struct amdgpu_device *adev) in soc15_read_disabled_bios() argument
404 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in soc15_read_indexed_register() argument
409 mutex_lock(&adev->grbm_idx_mutex); in soc15_read_indexed_register()
411 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in soc15_read_indexed_register()
416 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in soc15_read_indexed_register()
417 mutex_unlock(&adev->grbm_idx_mutex); in soc15_read_indexed_register()
421 static uint32_t soc15_get_register_value(struct amdgpu_device *adev, in soc15_get_register_value() argument
426 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc15_get_register_value()
429 return adev->gfx.config.gb_addr_config; in soc15_get_register_value()
431 return adev->gfx.config.db_debug2; in soc15_get_register_value()
436 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, in soc15_read_register() argument
445 if (!adev->reg_offset[en->hwip][en->inst]) in soc15_read_register()
447 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in soc15_read_register()
451 *value = soc15_get_register_value(adev, in soc15_read_register()
471 void soc15_program_register_sequence(struct amdgpu_device *adev, in soc15_program_register_sequence() argument
481 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; in soc15_program_register_sequence()
506 static int soc15_asic_baco_reset(struct amdgpu_device *adev) in soc15_asic_baco_reset() argument
508 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in soc15_asic_baco_reset()
512 if (ras && adev->ras_enabled) in soc15_asic_baco_reset()
513 adev->nbio.funcs->enable_doorbell_interrupt(adev, false); in soc15_asic_baco_reset()
515 ret = amdgpu_dpm_baco_reset(adev); in soc15_asic_baco_reset()
520 if (ras && adev->ras_enabled) in soc15_asic_baco_reset()
521 adev->nbio.funcs->enable_doorbell_interrupt(adev, true); in soc15_asic_baco_reset()
527 soc15_asic_reset_method(struct amdgpu_device *adev) in soc15_asic_reset_method() argument
531 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in soc15_asic_reset_method()
533 if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu) in soc15_asic_reset_method()
547 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", in soc15_asic_reset_method()
550 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in soc15_asic_reset_method()
558 if (adev->asic_type == CHIP_VEGA20) { in soc15_asic_reset_method()
559 if (adev->psp.sos.fw_version >= 0x80067) in soc15_asic_reset_method()
560 baco_reset = amdgpu_dpm_is_baco_supported(adev); in soc15_asic_reset_method()
565 if (ras && adev->ras_enabled && in soc15_asic_reset_method()
566 adev->pm.fw_version <= 0x283400) in soc15_asic_reset_method()
569 baco_reset = amdgpu_dpm_is_baco_supported(adev); in soc15_asic_reset_method()
587 if (adev->pcie_reset_ctx.in_link_reset) in soc15_asic_reset_method()
591 else if (!(adev->flags & AMD_IS_APU)) in soc15_asic_reset_method()
605 static bool soc15_need_reset_on_resume(struct amdgpu_device *adev) in soc15_need_reset_on_resume() argument
611 if (adev->in_s3 && !pm_resume_via_firmware()) in soc15_need_reset_on_resume()
617 static int soc15_asic_reset(struct amdgpu_device *adev) in soc15_asic_reset() argument
625 if ((adev->apu_flags & AMD_APU_IS_PICASSO || in soc15_asic_reset()
626 !(adev->apu_flags & AMD_APU_IS_RAVEN)) && in soc15_asic_reset()
627 soc15_need_reset_on_resume(adev)) in soc15_asic_reset()
630 if ((adev->apu_flags & AMD_APU_IS_RAVEN) || in soc15_asic_reset()
631 (adev->apu_flags & AMD_APU_IS_RAVEN2)) in soc15_asic_reset()
635 switch (soc15_asic_reset_method(adev)) { in soc15_asic_reset()
637 dev_info(adev->dev, "PCI reset\n"); in soc15_asic_reset()
638 return amdgpu_device_pci_reset(adev); in soc15_asic_reset()
640 dev_info(adev->dev, "BACO reset\n"); in soc15_asic_reset()
641 return soc15_asic_baco_reset(adev); in soc15_asic_reset()
643 dev_info(adev->dev, "MODE2 reset\n"); in soc15_asic_reset()
644 return amdgpu_dpm_mode2_reset(adev); in soc15_asic_reset()
646 dev_info(adev->dev, "Link reset\n"); in soc15_asic_reset()
647 return amdgpu_device_link_reset(adev); in soc15_asic_reset()
649 dev_info(adev->dev, "MODE1 reset\n"); in soc15_asic_reset()
650 return amdgpu_device_mode1_reset(adev); in soc15_asic_reset()
654 static int soc15_supports_baco(struct amdgpu_device *adev) in soc15_supports_baco() argument
656 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in soc15_supports_baco()
659 if (adev->asic_type == CHIP_VEGA20) { in soc15_supports_baco()
660 if (adev->psp.sos.fw_version >= 0x80067) in soc15_supports_baco()
661 return amdgpu_dpm_is_baco_supported(adev); in soc15_supports_baco()
664 return amdgpu_dpm_is_baco_supported(adev); in soc15_supports_baco()
678 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in soc15_set_uvd_clocks() argument
691 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in soc15_set_vce_clocks() argument
698 static void soc15_program_aspm(struct amdgpu_device *adev) in soc15_program_aspm() argument
700 if (!amdgpu_device_should_use_aspm(adev)) in soc15_program_aspm()
703 if (adev->nbio.funcs->program_aspm) in soc15_program_aspm()
704 adev->nbio.funcs->program_aspm(adev); in soc15_program_aspm()
716 static void soc15_reg_base_init(struct amdgpu_device *adev) in soc15_reg_base_init() argument
719 switch (adev->asic_type) { in soc15_reg_base_init()
724 vega10_reg_base_init(adev); in soc15_reg_base_init()
727 vega20_reg_base_init(adev); in soc15_reg_base_init()
730 arct_reg_base_init(adev); in soc15_reg_base_init()
733 aldebaran_reg_base_init(adev); in soc15_reg_base_init()
736 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type); in soc15_reg_base_init()
741 void soc15_set_virt_ops(struct amdgpu_device *adev) in soc15_set_virt_ops() argument
743 adev->virt.ops = &xgpu_ai_virt_ops; in soc15_set_virt_ops()
748 soc15_reg_base_init(adev); in soc15_set_virt_ops()
751 static bool soc15_need_full_reset(struct amdgpu_device *adev) in soc15_need_full_reset() argument
757 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, in soc15_get_pcie_usage() argument
767 if (adev->flags & AMD_IS_APU) in soc15_get_pcie_usage()
804 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, in vega20_get_pcie_usage() argument
814 if (adev->flags & AMD_IS_APU) in vega20_get_pcie_usage()
853 static bool soc15_need_reset_on_init(struct amdgpu_device *adev) in soc15_need_reset_on_init() argument
858 if (adev->asic_type == CHIP_RENOIR) in soc15_need_reset_on_init()
861 if (amdgpu_gmc_need_reset_on_init(adev)) in soc15_need_reset_on_init()
863 if (amdgpu_psp_tos_reload_needed(adev)) in soc15_need_reset_on_init()
868 if (!amdgpu_passthrough(adev)) in soc15_need_reset_on_init()
871 if (adev->flags & AMD_IS_APU) in soc15_need_reset_on_init()
884 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev) in soc15_get_pcie_replay_count() argument
896 static void soc15_pre_asic_init(struct amdgpu_device *adev) in soc15_pre_asic_init() argument
898 gmc_v9_0_restore_registers(adev); in soc15_pre_asic_init()
967 struct amdgpu_device *adev = ip_block->adev; in soc15_common_early_init() local
969 adev->nbio.funcs->set_reg_remap(adev); in soc15_common_early_init()
970 adev->smc_rreg = NULL; in soc15_common_early_init()
971 adev->smc_wreg = NULL; in soc15_common_early_init()
972 adev->pcie_rreg = &amdgpu_device_indirect_rreg; in soc15_common_early_init()
973 adev->pcie_wreg = &amdgpu_device_indirect_wreg; in soc15_common_early_init()
974 adev->pcie_rreg_ext = &amdgpu_device_indirect_rreg_ext; in soc15_common_early_init()
975 adev->pcie_wreg_ext = &amdgpu_device_indirect_wreg_ext; in soc15_common_early_init()
976 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; in soc15_common_early_init()
977 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; in soc15_common_early_init()
978 adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext; in soc15_common_early_init()
979 adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext; in soc15_common_early_init()
980 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; in soc15_common_early_init()
981 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; in soc15_common_early_init()
982 adev->didt_rreg = &soc15_didt_rreg; in soc15_common_early_init()
983 adev->didt_wreg = &soc15_didt_wreg; in soc15_common_early_init()
984 adev->gc_cac_rreg = &soc15_gc_cac_rreg; in soc15_common_early_init()
985 adev->gc_cac_wreg = &soc15_gc_cac_wreg; in soc15_common_early_init()
986 adev->se_cac_rreg = &soc15_se_cac_rreg; in soc15_common_early_init()
987 adev->se_cac_wreg = &soc15_se_cac_wreg; in soc15_common_early_init()
989 adev->rev_id = amdgpu_device_get_rev_id(adev); in soc15_common_early_init()
990 adev->external_rev_id = 0xFF; in soc15_common_early_init()
994 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in soc15_common_early_init()
996 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
997 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1016 adev->pg_flags = 0; in soc15_common_early_init()
1017 adev->external_rev_id = 0x1; in soc15_common_early_init()
1020 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
1021 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1039 adev->pg_flags = 0; in soc15_common_early_init()
1040 adev->external_rev_id = adev->rev_id + 0x14; in soc15_common_early_init()
1043 adev->asic_funcs = &vega20_asic_funcs; in soc15_common_early_init()
1044 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1062 adev->pg_flags = 0; in soc15_common_early_init()
1063 adev->external_rev_id = adev->rev_id + 0x28; in soc15_common_early_init()
1067 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
1069 if (adev->rev_id >= 0x8) in soc15_common_early_init()
1070 adev->apu_flags |= AMD_APU_IS_RAVEN2; in soc15_common_early_init()
1072 if (adev->apu_flags & AMD_APU_IS_RAVEN2) in soc15_common_early_init()
1073 adev->external_rev_id = adev->rev_id + 0x79; in soc15_common_early_init()
1074 else if (adev->apu_flags & AMD_APU_IS_PICASSO) in soc15_common_early_init()
1075 adev->external_rev_id = adev->rev_id + 0x41; in soc15_common_early_init()
1076 else if (adev->rev_id == 1) in soc15_common_early_init()
1077 adev->external_rev_id = adev->rev_id + 0x20; in soc15_common_early_init()
1079 adev->external_rev_id = adev->rev_id + 0x01; in soc15_common_early_init()
1081 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { in soc15_common_early_init()
1082 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1097 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; in soc15_common_early_init()
1098 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) { in soc15_common_early_init()
1099 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1117 adev->pg_flags = AMD_PG_SUPPORT_SDMA | in soc15_common_early_init()
1120 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1139 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; in soc15_common_early_init()
1143 adev->asic_funcs = &vega20_asic_funcs; in soc15_common_early_init()
1144 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1158 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG; in soc15_common_early_init()
1159 adev->external_rev_id = adev->rev_id + 0x32; in soc15_common_early_init()
1162 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
1164 if (adev->apu_flags & AMD_APU_IS_RENOIR) in soc15_common_early_init()
1165 adev->external_rev_id = adev->rev_id + 0x91; in soc15_common_early_init()
1167 adev->external_rev_id = adev->rev_id + 0xa1; in soc15_common_early_init()
1168 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1187 adev->pg_flags = AMD_PG_SUPPORT_SDMA | in soc15_common_early_init()
1193 adev->asic_funcs = &vega20_asic_funcs; in soc15_common_early_init()
1194 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1202 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; in soc15_common_early_init()
1203 adev->external_rev_id = adev->rev_id + 0x3c; in soc15_common_early_init()
1208 adev->asic_funcs = &aqua_vanjaram_asic_funcs; in soc15_common_early_init()
1209 adev->cg_flags = in soc15_common_early_init()
1215 adev->pg_flags = in soc15_common_early_init()
1220 adev->external_rev_id = adev->rev_id + 0x46; in soc15_common_early_init()
1221 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) in soc15_common_early_init()
1222 adev->external_rev_id = adev->rev_id + 0x50; in soc15_common_early_init()
1229 if (amdgpu_sriov_vf(adev)) { in soc15_common_early_init()
1230 amdgpu_virt_init_setting(adev); in soc15_common_early_init()
1231 xgpu_ai_mailbox_set_irq_funcs(adev); in soc15_common_early_init()
1239 struct amdgpu_device *adev = ip_block->adev; in soc15_common_late_init() local
1241 if (amdgpu_sriov_vf(adev)) in soc15_common_late_init()
1242 xgpu_ai_mailbox_get_irq(adev); in soc15_common_late_init()
1247 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); in soc15_common_late_init()
1254 struct amdgpu_device *adev = ip_block->adev; in soc15_common_sw_init() local
1256 if (amdgpu_sriov_vf(adev)) in soc15_common_sw_init()
1257 xgpu_ai_mailbox_add_irq_id(adev); in soc15_common_sw_init()
1259 if (adev->df.funcs && in soc15_common_sw_init()
1260 adev->df.funcs->sw_init) in soc15_common_sw_init()
1261 adev->df.funcs->sw_init(adev); in soc15_common_sw_init()
1268 struct amdgpu_device *adev = ip_block->adev; in soc15_common_sw_fini() local
1270 if (adev->df.funcs && in soc15_common_sw_fini()
1271 adev->df.funcs->sw_fini) in soc15_common_sw_fini()
1272 adev->df.funcs->sw_fini(adev); in soc15_common_sw_fini()
1276 static void soc15_sdma_doorbell_range_init(struct amdgpu_device *adev) in soc15_sdma_doorbell_range_init() argument
1281 if (!amdgpu_sriov_vf(adev)) { in soc15_sdma_doorbell_range_init()
1282 for (i = 0; i < adev->sdma.num_instances; i++) { in soc15_sdma_doorbell_range_init()
1283 adev->nbio.funcs->sdma_doorbell_range(adev, i, in soc15_sdma_doorbell_range_init()
1284 true, adev->doorbell_index.sdma_engine[i] << 1, in soc15_sdma_doorbell_range_init()
1285 adev->doorbell_index.sdma_doorbell_range); in soc15_sdma_doorbell_range_init()
1292 struct amdgpu_device *adev = ip_block->adev; in soc15_common_hw_init() local
1295 soc15_program_aspm(adev); in soc15_common_hw_init()
1297 adev->nbio.funcs->init_registers(adev); in soc15_common_hw_init()
1302 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) in soc15_common_hw_init()
1303 adev->nbio.funcs->remap_hdp_registers(adev); in soc15_common_hw_init()
1306 adev->nbio.funcs->enable_doorbell_aperture(adev, true); in soc15_common_hw_init()
1314 soc15_sdma_doorbell_range_init(adev); in soc15_common_hw_init()
1321 struct amdgpu_device *adev = ip_block->adev; in soc15_common_hw_fini() local
1328 adev->nbio.funcs->enable_doorbell_aperture(adev, false); in soc15_common_hw_fini()
1329 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); in soc15_common_hw_fini()
1331 if (amdgpu_sriov_vf(adev)) in soc15_common_hw_fini()
1332 xgpu_ai_mailbox_put_irq(adev); in soc15_common_hw_fini()
1338 if ((!amdgpu_sriov_vf(adev)) && in soc15_common_hw_fini()
1339 (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) && in soc15_common_hw_fini()
1340 adev->nbio.ras_if && in soc15_common_hw_fini()
1341 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) { in soc15_common_hw_fini()
1342 if (adev->nbio.ras && in soc15_common_hw_fini()
1343 adev->nbio.ras->init_ras_controller_interrupt) in soc15_common_hw_fini()
1344 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0); in soc15_common_hw_fini()
1345 if (adev->nbio.ras && in soc15_common_hw_fini()
1346 adev->nbio.ras->init_ras_err_event_athub_interrupt) in soc15_common_hw_fini()
1347 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); in soc15_common_hw_fini()
1360 struct amdgpu_device *adev = ip_block->adev; in soc15_common_resume() local
1362 if (soc15_need_reset_on_resume(adev)) { in soc15_common_resume()
1363 dev_info(adev->dev, "S3 suspend abort case, let's reset ASIC.\n"); in soc15_common_resume()
1364 soc15_asic_reset(adev); in soc15_common_resume()
1374 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) in soc15_update_drm_clock_gating() argument
1380 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) in soc15_update_drm_clock_gating()
1403 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) in soc15_update_drm_light_sleep() argument
1409 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) in soc15_update_drm_light_sleep()
1421 struct amdgpu_device *adev = ip_block->adev; in soc15_common_set_clockgating_state() local
1423 if (amdgpu_sriov_vf(adev)) in soc15_common_set_clockgating_state()
1426 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in soc15_common_set_clockgating_state()
1430 adev->nbio.funcs->update_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
1432 adev->nbio.funcs->update_medium_grain_light_sleep(adev, in soc15_common_set_clockgating_state()
1434 adev->hdp.funcs->update_clock_gating(adev, in soc15_common_set_clockgating_state()
1436 soc15_update_drm_clock_gating(adev, in soc15_common_set_clockgating_state()
1438 soc15_update_drm_light_sleep(adev, in soc15_common_set_clockgating_state()
1440 adev->smuio.funcs->update_rom_clock_gating(adev, in soc15_common_set_clockgating_state()
1442 adev->df.funcs->update_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
1448 adev->nbio.funcs->update_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
1450 adev->nbio.funcs->update_medium_grain_light_sleep(adev, in soc15_common_set_clockgating_state()
1452 adev->hdp.funcs->update_clock_gating(adev, in soc15_common_set_clockgating_state()
1454 soc15_update_drm_clock_gating(adev, in soc15_common_set_clockgating_state()
1456 soc15_update_drm_light_sleep(adev, in soc15_common_set_clockgating_state()
1461 adev->hdp.funcs->update_clock_gating(adev, in soc15_common_set_clockgating_state()
1472 struct amdgpu_device *adev = ip_block->adev; in soc15_common_get_clockgating_state() local
1475 if (amdgpu_sriov_vf(adev)) in soc15_common_get_clockgating_state()
1478 if (adev->nbio.funcs && adev->nbio.funcs->get_clockgating_state) in soc15_common_get_clockgating_state()
1479 adev->nbio.funcs->get_clockgating_state(adev, flags); in soc15_common_get_clockgating_state()
1481 if (adev->hdp.funcs && adev->hdp.funcs->get_clock_gating_state) in soc15_common_get_clockgating_state()
1482 adev->hdp.funcs->get_clock_gating_state(adev, flags); in soc15_common_get_clockgating_state()
1484 if ((amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) && in soc15_common_get_clockgating_state()
1485 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) && in soc15_common_get_clockgating_state()
1486 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 12)) && in soc15_common_get_clockgating_state()
1487 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 14))) { in soc15_common_get_clockgating_state()
1500 if (adev->smuio.funcs && adev->smuio.funcs->get_clock_gating_state) in soc15_common_get_clockgating_state()
1501 adev->smuio.funcs->get_clock_gating_state(adev, flags); in soc15_common_get_clockgating_state()
1503 if (adev->df.funcs && adev->df.funcs->get_clockgating_state) in soc15_common_get_clockgating_state()
1504 adev->df.funcs->get_clockgating_state(adev, flags); in soc15_common_get_clockgating_state()