Lines Matching refs:ip
28 #define GET_INST(ip, inst) \ argument
30 adev->ip_map.logical_to_dev_inst(adev, ip##_HWIP, inst) : inst)
31 #define GET_MASK(ip, mask) \ argument
33 adev->ip_map.logical_to_dev_mask(adev, ip##_HWIP, mask) : mask)
36 #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) argument
37 #define SOC15_REG_OFFSET1(ip, inst, reg, offset) \ argument
38 (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)+(offset))
50 #define WREG32_FIELD15(ip, idx, reg, field, val) \ argument
51 __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
53 adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
54 0, ip##_HWIP, idx) & \
56 0, ip##_HWIP, idx)
58 #define WREG32_FIELD15_PREREG(ip, idx, reg_name, field, val) \ argument
59 …__WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, …
61 adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, \
62 0, ip##_HWIP, idx) & \
64 0, ip##_HWIP, idx)
66 #define RREG32_SOC15(ip, inst, reg) \ argument
67 __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
68 0, ip##_HWIP, inst)
70 #define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP, 0) argument
72 #define RREG32_SOC15_IP_NO_KIQ(ip, reg, inst) __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ, ip##_HW… argument
74 #define RREG32_SOC15_NO_KIQ(ip, inst, reg) \ argument
75 __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
76 AMDGPU_REGS_NO_KIQ, ip##_HWIP, inst)
78 #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \ argument
79 __RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)) + \
80 (offset), 0, ip##_HWIP, inst)
82 #define WREG32_SOC15(ip, inst, reg, value) \ argument
83 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \
84 value, 0, ip##_HWIP, inst)
86 #define WREG32_SOC15_IP(ip, reg, value) \ argument
87 __WREG32_SOC15_RLC__(reg, value, 0, ip##_HWIP, 0)
89 #define WREG32_SOC15_IP_NO_KIQ(ip, reg, value, inst) \ argument
90 __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ, ip##_HWIP, inst)
92 #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \ argument
93 __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
94 value, AMDGPU_REGS_NO_KIQ, ip##_HWIP, inst)
96 #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \ argument
97 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, \
98 value, 0, ip##_HWIP, inst)
100 #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \ argument
102 (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)), \
105 #define SOC15_WAIT_ON_RREG_OFFSET(ip, inst, reg, offset, expected_value, mask) \ argument
107 (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg) + (offset)), \
138 #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \ argument
139 …__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value, AMDGPU_REGS…
151 #define WREG32_SOC15_RLC_SHADOW_EX(prefix, ip, inst, reg, value) \ argument
153 uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\
169 #define RREG32_SOC15_RLC(ip, inst, reg) \ argument
170 …__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, AMDGPU_REGS_RLC, ip#…
172 #define WREG32_SOC15_RLC(ip, inst, reg, value) \ argument
174 uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\
175 __WREG32_SOC15_RLC__(target_reg, value, AMDGPU_REGS_RLC, ip##_HWIP, inst); \
178 #define WREG32_SOC15_RLC_EX(prefix, ip, inst, reg, value) \ argument
184 #define WREG32_FIELD15_RLC(ip, idx, reg, field, val) \ argument
185 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \
186 (__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
187 AMDGPU_REGS_RLC, ip##_HWIP, idx) & \
189 AMDGPU_REGS_RLC, ip##_HWIP, idx)
191 #define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \ argument
192 …_WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value, AMD…
194 #define RREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset) \ argument
195 …__RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, AMDGPU_RE…
198 #define RREG32_SOC15_EXT(ip, inst, reg, ext) \ argument
199 RREG32_PCIE_EXT((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) * 4 \
202 #define WREG32_SOC15_EXT(ip, inst, reg, ext, value) \ argument
203 WREG32_PCIE_EXT((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) * 4 \