Lines Matching refs:adev
144 static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode, in soc21_query_video_codecs() argument
147 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) in soc21_query_video_codecs()
150 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { in soc21_query_video_codecs()
155 if (amdgpu_sriov_vf(adev)) { in soc21_query_video_codecs()
156 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) || in soc21_query_video_codecs()
157 !amdgpu_sriov_is_av1_support(adev)) { in soc21_query_video_codecs()
169 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)) { in soc21_query_video_codecs()
193 static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg) in soc21_didt_rreg() argument
201 spin_lock_irqsave(&adev->didt_idx_lock, flags); in soc21_didt_rreg()
204 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in soc21_didt_rreg()
208 static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc21_didt_wreg() argument
215 spin_lock_irqsave(&adev->didt_idx_lock, flags); in soc21_didt_wreg()
218 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in soc21_didt_wreg()
221 static u32 soc21_get_config_memsize(struct amdgpu_device *adev) in soc21_get_config_memsize() argument
223 return adev->nbio.funcs->get_memsize(adev); in soc21_get_config_memsize()
226 static u32 soc21_get_xclk(struct amdgpu_device *adev) in soc21_get_xclk() argument
228 return adev->clock.spll.reference_freq; in soc21_get_xclk()
232 void soc21_grbm_select(struct amdgpu_device *adev, in soc21_grbm_select() argument
244 static bool soc21_read_disabled_bios(struct amdgpu_device *adev) in soc21_read_disabled_bios() argument
272 static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in soc21_read_indexed_register() argument
277 mutex_lock(&adev->grbm_idx_mutex); in soc21_read_indexed_register()
279 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in soc21_read_indexed_register()
284 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in soc21_read_indexed_register()
285 mutex_unlock(&adev->grbm_idx_mutex); in soc21_read_indexed_register()
289 static uint32_t soc21_get_register_value(struct amdgpu_device *adev, in soc21_get_register_value() argument
294 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc21_get_register_value()
296 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config) in soc21_get_register_value()
297 return adev->gfx.config.gb_addr_config; in soc21_get_register_value()
302 static int soc21_read_register(struct amdgpu_device *adev, u32 se_num, in soc21_read_register() argument
311 if (!adev->reg_offset[en->hwip][en->inst]) in soc21_read_register()
313 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in soc21_read_register()
317 *value = soc21_get_register_value(adev, in soc21_read_register()
326 static int soc21_asic_mode1_reset(struct amdgpu_device *adev)
331 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
334 pci_clear_master(adev->pdev);
336 amdgpu_device_cache_pci_state(adev->pdev);
338 if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
339 dev_info(adev->dev, "GPU smu mode1 reset\n");
340 ret = amdgpu_dpm_mode1_reset(adev);
342 dev_info(adev->dev, "GPU psp mode1 reset\n");
343 ret = psp_gpu_reset(adev);
347 dev_err(adev->dev, "GPU mode1 reset failed\n");
348 amdgpu_device_load_pci_state(adev->pdev);
351 for (i = 0; i < adev->usec_timeout; i++) {
352 u32 memsize = adev->nbio.funcs->get_memsize(adev);
359 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
366 soc21_asic_reset_method(struct amdgpu_device *adev) in soc21_asic_reset_method() argument
374 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", in soc21_asic_reset_method()
377 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in soc21_asic_reset_method()
390 if (amdgpu_dpm_is_baco_supported(adev)) in soc21_asic_reset_method()
397 static int soc21_asic_reset(struct amdgpu_device *adev) in soc21_asic_reset() argument
401 switch (soc21_asic_reset_method(adev)) { in soc21_asic_reset()
403 dev_info(adev->dev, "PCI reset\n"); in soc21_asic_reset()
404 ret = amdgpu_device_pci_reset(adev); in soc21_asic_reset()
407 dev_info(adev->dev, "BACO reset\n"); in soc21_asic_reset()
408 ret = amdgpu_dpm_baco_reset(adev); in soc21_asic_reset()
411 dev_info(adev->dev, "MODE2 reset\n"); in soc21_asic_reset()
412 ret = amdgpu_dpm_mode2_reset(adev); in soc21_asic_reset()
415 dev_info(adev->dev, "MODE1 reset\n"); in soc21_asic_reset()
416 ret = amdgpu_device_mode1_reset(adev); in soc21_asic_reset()
423 static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in soc21_set_uvd_clocks() argument
429 static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in soc21_set_vce_clocks() argument
435 static void soc21_program_aspm(struct amdgpu_device *adev) in soc21_program_aspm() argument
437 if (!amdgpu_device_should_use_aspm(adev)) in soc21_program_aspm()
440 if (adev->nbio.funcs->program_aspm) in soc21_program_aspm()
441 adev->nbio.funcs->program_aspm(adev); in soc21_program_aspm()
452 static bool soc21_need_full_reset(struct amdgpu_device *adev) in soc21_need_full_reset() argument
454 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in soc21_need_full_reset()
463 static bool soc21_need_reset_on_init(struct amdgpu_device *adev) in soc21_need_reset_on_init() argument
467 if (adev->flags & AMD_IS_APU) in soc21_need_reset_on_init()
480 static void soc21_init_doorbell_index(struct amdgpu_device *adev) in soc21_init_doorbell_index() argument
482 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; in soc21_init_doorbell_index()
483 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; in soc21_init_doorbell_index()
484 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; in soc21_init_doorbell_index()
485 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; in soc21_init_doorbell_index()
486 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; in soc21_init_doorbell_index()
487 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; in soc21_init_doorbell_index()
488 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; in soc21_init_doorbell_index()
489 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; in soc21_init_doorbell_index()
490 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; in soc21_init_doorbell_index()
491 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; in soc21_init_doorbell_index()
492 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; in soc21_init_doorbell_index()
493 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; in soc21_init_doorbell_index()
494 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; in soc21_init_doorbell_index()
495 adev->doorbell_index.gfx_userqueue_start = in soc21_init_doorbell_index()
497 adev->doorbell_index.gfx_userqueue_end = in soc21_init_doorbell_index()
499 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; in soc21_init_doorbell_index()
500 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; in soc21_init_doorbell_index()
501 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; in soc21_init_doorbell_index()
502 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; in soc21_init_doorbell_index()
503 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; in soc21_init_doorbell_index()
504 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; in soc21_init_doorbell_index()
505 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; in soc21_init_doorbell_index()
506 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; in soc21_init_doorbell_index()
507 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; in soc21_init_doorbell_index()
508 adev->doorbell_index.vpe_ring = AMDGPU_NAVI10_DOORBELL64_VPE; in soc21_init_doorbell_index()
509 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; in soc21_init_doorbell_index()
510 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; in soc21_init_doorbell_index()
512 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; in soc21_init_doorbell_index()
513 adev->doorbell_index.sdma_doorbell_range = 20; in soc21_init_doorbell_index()
516 static void soc21_pre_asic_init(struct amdgpu_device *adev) in soc21_pre_asic_init() argument
520 static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev, in soc21_update_umd_stable_pstate() argument
524 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); in soc21_update_umd_stable_pstate()
526 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); in soc21_update_umd_stable_pstate()
528 if (adev->gfx.funcs->update_perfmon_mgcg) in soc21_update_umd_stable_pstate()
529 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); in soc21_update_umd_stable_pstate()
556 struct amdgpu_device *adev = ip_block->adev; in soc21_common_early_init() local
558 adev->nbio.funcs->set_reg_remap(adev); in soc21_common_early_init()
559 adev->smc_rreg = NULL; in soc21_common_early_init()
560 adev->smc_wreg = NULL; in soc21_common_early_init()
561 adev->pcie_rreg = &amdgpu_device_indirect_rreg; in soc21_common_early_init()
562 adev->pcie_wreg = &amdgpu_device_indirect_wreg; in soc21_common_early_init()
563 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; in soc21_common_early_init()
564 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; in soc21_common_early_init()
565 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; in soc21_common_early_init()
566 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; in soc21_common_early_init()
569 adev->uvd_ctx_rreg = NULL; in soc21_common_early_init()
570 adev->uvd_ctx_wreg = NULL; in soc21_common_early_init()
572 adev->didt_rreg = &soc21_didt_rreg; in soc21_common_early_init()
573 adev->didt_wreg = &soc21_didt_wreg; in soc21_common_early_init()
575 adev->asic_funcs = &soc21_asic_funcs; in soc21_common_early_init()
577 adev->rev_id = amdgpu_device_get_rev_id(adev); in soc21_common_early_init()
578 adev->external_rev_id = 0xff; in soc21_common_early_init()
579 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in soc21_common_early_init()
581 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | in soc21_common_early_init()
599 adev->pg_flags = AMD_PG_SUPPORT_VCN | in soc21_common_early_init()
604 adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update in soc21_common_early_init()
607 adev->cg_flags = in soc21_common_early_init()
617 adev->pg_flags = in soc21_common_early_init()
623 adev->external_rev_id = adev->rev_id + 0x10; in soc21_common_early_init()
626 adev->cg_flags = in soc21_common_early_init()
644 adev->pg_flags = in soc21_common_early_init()
649 adev->external_rev_id = adev->rev_id + 0x1; in soc21_common_early_init()
652 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | in soc21_common_early_init()
661 adev->pg_flags = AMD_PG_SUPPORT_VCN | in soc21_common_early_init()
664 adev->external_rev_id = adev->rev_id + 0x20; in soc21_common_early_init()
667 adev->cg_flags = in soc21_common_early_init()
685 adev->pg_flags = AMD_PG_SUPPORT_VCN | in soc21_common_early_init()
689 adev->external_rev_id = adev->rev_id + 0x80; in soc21_common_early_init()
692 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | in soc21_common_early_init()
712 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | in soc21_common_early_init()
717 if (adev->rev_id == 0) in soc21_common_early_init()
718 adev->external_rev_id = 0x1; in soc21_common_early_init()
720 adev->external_rev_id = adev->rev_id + 0x10; in soc21_common_early_init()
723 adev->cg_flags = in soc21_common_early_init()
744 adev->pg_flags = in soc21_common_early_init()
749 adev->external_rev_id = adev->rev_id + 0xc1; in soc21_common_early_init()
752 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | in soc21_common_early_init()
772 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | in soc21_common_early_init()
777 adev->external_rev_id = adev->rev_id + 0x40; in soc21_common_early_init()
780 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | in soc21_common_early_init()
800 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | in soc21_common_early_init()
805 adev->external_rev_id = adev->rev_id + 0x50; in soc21_common_early_init()
812 if (amdgpu_sriov_vf(adev)) { in soc21_common_early_init()
813 amdgpu_virt_init_setting(adev); in soc21_common_early_init()
814 xgpu_nv_mailbox_set_irq_funcs(adev); in soc21_common_early_init()
822 struct amdgpu_device *adev = ip_block->adev; in soc21_common_late_init() local
824 if (amdgpu_sriov_vf(adev)) { in soc21_common_late_init()
825 xgpu_nv_mailbox_get_irq(adev); in soc21_common_late_init()
826 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) || in soc21_common_late_init()
827 !amdgpu_sriov_is_av1_support(adev)) { in soc21_common_late_init()
828 amdgpu_virt_update_sriov_video_codec(adev, in soc21_common_late_init()
834 amdgpu_virt_update_sriov_video_codec(adev, in soc21_common_late_init()
841 if (adev->nbio.ras && in soc21_common_late_init()
842 adev->nbio.ras_err_event_athub_irq.funcs) in soc21_common_late_init()
847 amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0); in soc21_common_late_init()
853 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); in soc21_common_late_init()
860 struct amdgpu_device *adev = ip_block->adev; in soc21_common_sw_init() local
862 if (amdgpu_sriov_vf(adev)) in soc21_common_sw_init()
863 xgpu_nv_mailbox_add_irq_id(adev); in soc21_common_sw_init()
870 struct amdgpu_device *adev = ip_block->adev; in soc21_common_hw_init() local
873 soc21_program_aspm(adev); in soc21_common_hw_init()
875 adev->nbio.funcs->init_registers(adev); in soc21_common_hw_init()
880 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) in soc21_common_hw_init()
881 adev->nbio.funcs->remap_hdp_registers(adev); in soc21_common_hw_init()
883 adev->nbio.funcs->enable_doorbell_aperture(adev, true); in soc21_common_hw_init()
890 struct amdgpu_device *adev = ip_block->adev; in soc21_common_hw_fini() local
897 adev->nbio.funcs->enable_doorbell_aperture(adev, false); in soc21_common_hw_fini()
898 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); in soc21_common_hw_fini()
900 if (amdgpu_sriov_vf(adev)) { in soc21_common_hw_fini()
901 xgpu_nv_mailbox_put_irq(adev); in soc21_common_hw_fini()
903 if (adev->nbio.ras && in soc21_common_hw_fini()
904 adev->nbio.ras_err_event_athub_irq.funcs) in soc21_common_hw_fini()
905 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); in soc21_common_hw_fini()
916 static bool soc21_need_reset_on_resume(struct amdgpu_device *adev) in soc21_need_reset_on_resume() argument
926 if (!(adev->flags & AMD_IS_APU) && adev->in_s3) { in soc21_need_reset_on_resume()
939 struct amdgpu_device *adev = ip_block->adev; in soc21_common_resume() local
941 if (soc21_need_reset_on_resume(adev)) { in soc21_common_resume()
942 dev_info(adev->dev, "S3 suspend aborted, resetting..."); in soc21_common_resume()
943 soc21_asic_reset(adev); in soc21_common_resume()
957 struct amdgpu_device *adev = ip_block->adev; in soc21_common_set_clockgating_state() local
959 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in soc21_common_set_clockgating_state()
968 adev->nbio.funcs->update_medium_grain_clock_gating(adev, in soc21_common_set_clockgating_state()
970 adev->nbio.funcs->update_medium_grain_light_sleep(adev, in soc21_common_set_clockgating_state()
972 adev->hdp.funcs->update_clock_gating(adev, in soc21_common_set_clockgating_state()
984 struct amdgpu_device *adev = ip_block->adev; in soc21_common_set_powergating_state() local
986 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { in soc21_common_set_powergating_state()
989 adev->lsdma.funcs->update_memory_power_gating(adev, in soc21_common_set_powergating_state()
1001 struct amdgpu_device *adev = ip_block->adev; in soc21_common_get_clockgating_state() local
1003 adev->nbio.funcs->get_clockgating_state(adev, flags); in soc21_common_get_clockgating_state()
1005 adev->hdp.funcs->get_clock_gating_state(adev, flags); in soc21_common_get_clockgating_state()