Lines Matching refs:adev
73 static int soc24_query_video_codecs(struct amdgpu_device *adev, bool encode, in soc24_query_video_codecs() argument
76 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) in soc24_query_video_codecs()
79 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { in soc24_query_video_codecs()
91 static u32 soc24_get_config_memsize(struct amdgpu_device *adev) in soc24_get_config_memsize() argument
93 return adev->nbio.funcs->get_memsize(adev); in soc24_get_config_memsize()
96 static u32 soc24_get_xclk(struct amdgpu_device *adev) in soc24_get_xclk() argument
98 return adev->clock.spll.reference_freq; in soc24_get_xclk()
101 void soc24_grbm_select(struct amdgpu_device *adev, in soc24_grbm_select() argument
135 static uint32_t soc24_read_indexed_register(struct amdgpu_device *adev, in soc24_read_indexed_register() argument
142 mutex_lock(&adev->grbm_idx_mutex); in soc24_read_indexed_register()
144 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in soc24_read_indexed_register()
149 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in soc24_read_indexed_register()
150 mutex_unlock(&adev->grbm_idx_mutex); in soc24_read_indexed_register()
154 static uint32_t soc24_get_register_value(struct amdgpu_device *adev, in soc24_get_register_value() argument
159 return soc24_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc24_get_register_value()
162 adev->gfx.config.gb_addr_config) in soc24_get_register_value()
163 return adev->gfx.config.gb_addr_config; in soc24_get_register_value()
168 static int soc24_read_register(struct amdgpu_device *adev, u32 se_num, in soc24_read_register() argument
177 if (!adev->reg_offset[en->hwip][en->inst]) in soc24_read_register()
179 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in soc24_read_register()
183 *value = soc24_get_register_value(adev, in soc24_read_register()
192 soc24_asic_reset_method(struct amdgpu_device *adev) in soc24_asic_reset_method() argument
200 dev_warn(adev->dev, in soc24_asic_reset_method()
204 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in soc24_asic_reset_method()
209 if (amdgpu_dpm_is_baco_supported(adev)) in soc24_asic_reset_method()
216 static int soc24_asic_reset(struct amdgpu_device *adev) in soc24_asic_reset() argument
220 switch (soc24_asic_reset_method(adev)) { in soc24_asic_reset()
222 dev_info(adev->dev, "PCI reset\n"); in soc24_asic_reset()
223 ret = amdgpu_device_pci_reset(adev); in soc24_asic_reset()
226 dev_info(adev->dev, "BACO reset\n"); in soc24_asic_reset()
227 ret = amdgpu_dpm_baco_reset(adev); in soc24_asic_reset()
230 dev_info(adev->dev, "MODE2 reset\n"); in soc24_asic_reset()
231 ret = amdgpu_dpm_mode2_reset(adev); in soc24_asic_reset()
234 dev_info(adev->dev, "MODE1 reset\n"); in soc24_asic_reset()
235 ret = amdgpu_device_mode1_reset(adev); in soc24_asic_reset()
242 static void soc24_program_aspm(struct amdgpu_device *adev) in soc24_program_aspm() argument
244 if (!amdgpu_device_should_use_aspm(adev)) in soc24_program_aspm()
247 if (!(adev->flags & AMD_IS_APU) && in soc24_program_aspm()
248 (adev->nbio.funcs->program_aspm)) in soc24_program_aspm()
249 adev->nbio.funcs->program_aspm(adev); in soc24_program_aspm()
260 static bool soc24_need_full_reset(struct amdgpu_device *adev) in soc24_need_full_reset() argument
262 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in soc24_need_full_reset()
270 static bool soc24_need_reset_on_init(struct amdgpu_device *adev) in soc24_need_reset_on_init() argument
274 if (adev->flags & AMD_IS_APU) in soc24_need_reset_on_init()
287 static uint64_t soc24_get_pcie_replay_count(struct amdgpu_device *adev) in soc24_get_pcie_replay_count() argument
295 static void soc24_init_doorbell_index(struct amdgpu_device *adev) in soc24_init_doorbell_index() argument
297 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; in soc24_init_doorbell_index()
298 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; in soc24_init_doorbell_index()
299 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; in soc24_init_doorbell_index()
300 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; in soc24_init_doorbell_index()
301 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; in soc24_init_doorbell_index()
302 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; in soc24_init_doorbell_index()
303 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; in soc24_init_doorbell_index()
304 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; in soc24_init_doorbell_index()
305 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; in soc24_init_doorbell_index()
306 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; in soc24_init_doorbell_index()
307 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; in soc24_init_doorbell_index()
308 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; in soc24_init_doorbell_index()
309 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; in soc24_init_doorbell_index()
310 adev->doorbell_index.gfx_userqueue_start = in soc24_init_doorbell_index()
312 adev->doorbell_index.gfx_userqueue_end = in soc24_init_doorbell_index()
314 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; in soc24_init_doorbell_index()
315 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; in soc24_init_doorbell_index()
316 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; in soc24_init_doorbell_index()
317 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; in soc24_init_doorbell_index()
318 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; in soc24_init_doorbell_index()
319 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; in soc24_init_doorbell_index()
320 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; in soc24_init_doorbell_index()
321 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; in soc24_init_doorbell_index()
322 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; in soc24_init_doorbell_index()
323 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; in soc24_init_doorbell_index()
324 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; in soc24_init_doorbell_index()
326 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; in soc24_init_doorbell_index()
327 adev->doorbell_index.sdma_doorbell_range = 20; in soc24_init_doorbell_index()
330 static void soc24_pre_asic_init(struct amdgpu_device *adev) in soc24_pre_asic_init() argument
334 static int soc24_update_umd_stable_pstate(struct amdgpu_device *adev, in soc24_update_umd_stable_pstate() argument
338 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); in soc24_update_umd_stable_pstate()
340 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); in soc24_update_umd_stable_pstate()
342 if (adev->gfx.funcs->update_perfmon_mgcg) in soc24_update_umd_stable_pstate()
343 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); in soc24_update_umd_stable_pstate()
367 struct amdgpu_device *adev = ip_block->adev; in soc24_common_early_init() local
369 adev->nbio.funcs->set_reg_remap(adev); in soc24_common_early_init()
370 adev->smc_rreg = NULL; in soc24_common_early_init()
371 adev->smc_wreg = NULL; in soc24_common_early_init()
372 adev->pcie_rreg = &amdgpu_device_indirect_rreg; in soc24_common_early_init()
373 adev->pcie_wreg = &amdgpu_device_indirect_wreg; in soc24_common_early_init()
374 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; in soc24_common_early_init()
375 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; in soc24_common_early_init()
376 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; in soc24_common_early_init()
377 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; in soc24_common_early_init()
378 adev->uvd_ctx_rreg = NULL; in soc24_common_early_init()
379 adev->uvd_ctx_wreg = NULL; in soc24_common_early_init()
380 adev->didt_rreg = NULL; in soc24_common_early_init()
381 adev->didt_wreg = NULL; in soc24_common_early_init()
383 adev->asic_funcs = &soc24_asic_funcs; in soc24_common_early_init()
385 adev->rev_id = amdgpu_device_get_rev_id(adev); in soc24_common_early_init()
386 adev->external_rev_id = 0xff; in soc24_common_early_init()
388 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in soc24_common_early_init()
390 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | in soc24_common_early_init()
403 adev->pg_flags = AMD_PG_SUPPORT_VCN | in soc24_common_early_init()
406 adev->external_rev_id = adev->rev_id + 0x40; in soc24_common_early_init()
409 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | in soc24_common_early_init()
423 adev->pg_flags = AMD_PG_SUPPORT_VCN | in soc24_common_early_init()
427 adev->external_rev_id = adev->rev_id + 0x50; in soc24_common_early_init()
434 if (amdgpu_sriov_vf(adev)) { in soc24_common_early_init()
435 amdgpu_virt_init_setting(adev); in soc24_common_early_init()
436 xgpu_nv_mailbox_set_irq_funcs(adev); in soc24_common_early_init()
444 struct amdgpu_device *adev = ip_block->adev; in soc24_common_late_init() local
446 if (amdgpu_sriov_vf(adev)) { in soc24_common_late_init()
447 xgpu_nv_mailbox_get_irq(adev); in soc24_common_late_init()
449 if (adev->nbio.ras && in soc24_common_late_init()
450 adev->nbio.ras_err_event_athub_irq.funcs) in soc24_common_late_init()
456 amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0); in soc24_common_late_init()
462 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); in soc24_common_late_init()
469 struct amdgpu_device *adev = ip_block->adev; in soc24_common_sw_init() local
471 if (amdgpu_sriov_vf(adev)) in soc24_common_sw_init()
472 xgpu_nv_mailbox_add_irq_id(adev); in soc24_common_sw_init()
479 struct amdgpu_device *adev = ip_block->adev; in soc24_common_hw_init() local
482 soc24_program_aspm(adev); in soc24_common_hw_init()
484 adev->nbio.funcs->init_registers(adev); in soc24_common_hw_init()
489 if (adev->nbio.funcs->remap_hdp_registers) in soc24_common_hw_init()
490 adev->nbio.funcs->remap_hdp_registers(adev); in soc24_common_hw_init()
492 if (adev->df.funcs->hw_init) in soc24_common_hw_init()
493 adev->df.funcs->hw_init(adev); in soc24_common_hw_init()
496 adev->nbio.funcs->enable_doorbell_aperture(adev, true); in soc24_common_hw_init()
503 struct amdgpu_device *adev = ip_block->adev; in soc24_common_hw_fini() local
510 adev->nbio.funcs->enable_doorbell_aperture(adev, false); in soc24_common_hw_fini()
511 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); in soc24_common_hw_fini()
513 if (amdgpu_sriov_vf(adev)) { in soc24_common_hw_fini()
514 xgpu_nv_mailbox_put_irq(adev); in soc24_common_hw_fini()
516 if (adev->nbio.ras && in soc24_common_hw_fini()
517 adev->nbio.ras_err_event_athub_irq.funcs) in soc24_common_hw_fini()
518 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); in soc24_common_hw_fini()
542 struct amdgpu_device *adev = ip_block->adev; in soc24_common_set_clockgating_state() local
544 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in soc24_common_set_clockgating_state()
546 adev->nbio.funcs->update_medium_grain_clock_gating(adev, in soc24_common_set_clockgating_state()
548 adev->nbio.funcs->update_medium_grain_light_sleep(adev, in soc24_common_set_clockgating_state()
550 adev->hdp.funcs->update_clock_gating(adev, in soc24_common_set_clockgating_state()
562 struct amdgpu_device *adev = ip_block->adev; in soc24_common_set_powergating_state() local
564 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { in soc24_common_set_powergating_state()
567 adev->lsdma.funcs->update_memory_power_gating(adev, in soc24_common_set_powergating_state()
579 struct amdgpu_device *adev = ip_block->adev; in soc24_common_get_clockgating_state() local
581 adev->nbio.funcs->get_clockgating_state(adev, flags); in soc24_common_get_clockgating_state()
583 adev->hdp.funcs->get_clock_gating_state(adev, flags); in soc24_common_get_clockgating_state()