Lines Matching refs:PACKET0
174 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); in uvd_v4_2_hw_init()
178 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v4_2_hw_init()
182 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v4_2_hw_init()
187 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v4_2_hw_init()
190 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v4_2_hw_init()
482 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v4_2_ring_emit_fence()
484 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v4_2_ring_emit_fence()
486 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v4_2_ring_emit_fence()
488 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v4_2_ring_emit_fence()
491 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v4_2_ring_emit_fence()
493 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v4_2_ring_emit_fence()
495 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v4_2_ring_emit_fence()
518 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v4_2_ring_test_ring()
549 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0)); in uvd_v4_2_ring_emit_ib()
551 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); in uvd_v4_2_ring_emit_ib()
562 amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0)); in uvd_v4_2_ring_insert_nop()