Lines Matching refs:WREG32
88 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v5_0_ring_set_wptr()
286 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in uvd_v5_0_mc_resume()
288 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in uvd_v5_0_mc_resume()
293 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); in uvd_v5_0_mc_resume()
294 WREG32(mmUVD_VCPU_CACHE_SIZE0, size); in uvd_v5_0_mc_resume()
298 WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); in uvd_v5_0_mc_resume()
299 WREG32(mmUVD_VCPU_CACHE_SIZE1, size); in uvd_v5_0_mc_resume()
304 WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); in uvd_v5_0_mc_resume()
305 WREG32(mmUVD_VCPU_CACHE_SIZE2, size); in uvd_v5_0_mc_resume()
307 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v5_0_mc_resume()
308 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v5_0_mc_resume()
309 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v5_0_mc_resume()
344 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | in uvd_v5_0_start()
356 WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | in uvd_v5_0_start()
364 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); in uvd_v5_0_start()
365 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); in uvd_v5_0_start()
367 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); in uvd_v5_0_start()
368 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); in uvd_v5_0_start()
369 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); in uvd_v5_0_start()
370 WREG32(mmUVD_MPC_SET_MUXB1, 0x0); in uvd_v5_0_start()
371 WREG32(mmUVD_MPC_SET_ALU, 0); in uvd_v5_0_start()
372 WREG32(mmUVD_MPC_SET_MUX, 0x88); in uvd_v5_0_start()
375 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v5_0_start()
379 WREG32(mmUVD_VCPU_CNTL, 1 << 9); in uvd_v5_0_start()
385 WREG32(mmUVD_SOFT_RESET, 0); in uvd_v5_0_start()
428 WREG32(mmUVD_RBC_RB_CNTL, tmp); in uvd_v5_0_start()
431 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); in uvd_v5_0_start()
434 WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); in uvd_v5_0_start()
437 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, in uvd_v5_0_start()
439 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, in uvd_v5_0_start()
443 WREG32(mmUVD_RBC_RB_RPTR, 0); in uvd_v5_0_start()
446 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v5_0_start()
463 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); in uvd_v5_0_stop()
470 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v5_0_stop()
474 WREG32(mmUVD_VCPU_CNTL, 0x0); in uvd_v5_0_stop()
479 WREG32(mmUVD_STATUS, 0); in uvd_v5_0_stop()
528 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); in uvd_v5_0_ring_test_ring()
675 WREG32(mmUVD_SUVD_CGC_GATE, data1); in uvd_v5_0_enable_clock_gating()
676 WREG32(mmUVD_CGC_GATE, data3); in uvd_v5_0_enable_clock_gating()
722 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_set_sw_clock_gating()
723 WREG32(mmUVD_SUVD_CGC_CTRL, data2); in uvd_v5_0_set_sw_clock_gating()
762 WREG32(mmUVD_CGC_GATE, data);
763 WREG32(mmUVD_SUVD_CGC_GATE, data1);
780 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_enable_mgcg()
789 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_enable_mgcg()