Lines Matching refs:PACKET0
483 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); in uvd_v6_0_hw_init()
487 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v6_0_hw_init()
491 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v6_0_hw_init()
496 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v6_0_hw_init()
499 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v6_0_hw_init()
928 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v6_0_ring_emit_fence()
930 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v6_0_ring_emit_fence()
932 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v6_0_ring_emit_fence()
934 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v6_0_ring_emit_fence()
937 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v6_0_ring_emit_fence()
939 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v6_0_ring_emit_fence()
941 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v6_0_ring_emit_fence()
996 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v6_0_ring_test_ring()
1029 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID, 0)); in uvd_v6_0_ring_emit_ib()
1032 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); in uvd_v6_0_ring_emit_ib()
1034 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0)); in uvd_v6_0_ring_emit_ib()
1036 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); in uvd_v6_0_ring_emit_ib()
1067 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v6_0_ring_emit_wreg()
1069 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v6_0_ring_emit_wreg()
1071 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v6_0_ring_emit_wreg()
1080 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v6_0_ring_emit_vm_flush()
1082 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v6_0_ring_emit_vm_flush()
1084 amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0)); in uvd_v6_0_ring_emit_vm_flush()
1086 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v6_0_ring_emit_vm_flush()
1095 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v6_0_ring_emit_pipeline_sync()
1097 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v6_0_ring_emit_pipeline_sync()
1099 amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0)); in uvd_v6_0_ring_emit_pipeline_sync()
1101 amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH9, 0)); in uvd_v6_0_ring_emit_pipeline_sync()
1103 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v6_0_ring_emit_pipeline_sync()
1114 amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0)); in uvd_v6_0_ring_insert_nop()