Lines Matching refs:gpu_addr
694 lower_32_bits(adev->uvd.inst[i].gpu_addr)); in uvd_v7_0_mc_resume()
696 upper_32_bits(adev->uvd.inst[i].gpu_addr)); in uvd_v7_0_mc_resume()
705 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset)); in uvd_v7_0_mc_resume()
707 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset)); in uvd_v7_0_mc_resume()
712 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); in uvd_v7_0_mc_resume()
714 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); in uvd_v7_0_mc_resume()
734 uint64_t addr = table->gpu_addr; in uvd_v7_0_mmsch_start()
836 lower_32_bits(adev->uvd.inst[i].gpu_addr)); in uvd_v7_0_sriov_start()
838 upper_32_bits(adev->uvd.inst[i].gpu_addr)); in uvd_v7_0_sriov_start()
848 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset)); in uvd_v7_0_sriov_start()
850 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset)); in uvd_v7_0_sriov_start()
855 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); in uvd_v7_0_sriov_start()
857 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); in uvd_v7_0_sriov_start()
923 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), ring->gpu_addr); in uvd_v7_0_sriov_start()
924 …H_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr)); in uvd_v7_0_sriov_start()
1097 (upper_32_bits(ring->gpu_addr) >> 2)); in uvd_v7_0_start()
1101 lower_32_bits(ring->gpu_addr)); in uvd_v7_0_start()
1103 upper_32_bits(ring->gpu_addr)); in uvd_v7_0_start()
1118 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO, ring->gpu_addr); in uvd_v7_0_start()
1119 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in uvd_v7_0_start()
1125 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO2, ring->gpu_addr); in uvd_v7_0_start()
1126 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in uvd_v7_0_start()
1333 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in uvd_v7_0_ring_emit_ib()
1336 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in uvd_v7_0_ring_emit_ib()
1361 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in uvd_v7_0_enc_ring_emit_ib()
1362 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in uvd_v7_0_enc_ring_emit_ib()