Lines Matching refs:gpu_addr
364 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v1_0_mc_resume_spg_mode()
366 upper_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v1_0_mc_resume_spg_mode()
376 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v1_0_mc_resume_spg_mode()
378 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v1_0_mc_resume_spg_mode()
384 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v1_0_mc_resume_spg_mode()
386 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v1_0_mc_resume_spg_mode()
435 lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); in vcn_v1_0_mc_resume_dpg_mode()
437 upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); in vcn_v1_0_mc_resume_dpg_mode()
447 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); in vcn_v1_0_mc_resume_dpg_mode()
449 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); in vcn_v1_0_mc_resume_dpg_mode()
457 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), in vcn_v1_0_mc_resume_dpg_mode()
460 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), in vcn_v1_0_mc_resume_dpg_mode()
976 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v1_0_start_spg_mode()
980 lower_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
982 upper_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
999 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v1_0_start_spg_mode()
1000 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
1006 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v1_0_start_spg_mode()
1007 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
1140 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v1_0_start_dpg_mode()
1144 lower_32_bits(ring->gpu_addr)); in vcn_v1_0_start_dpg_mode()
1146 upper_32_bits(ring->gpu_addr)); in vcn_v1_0_start_dpg_mode()
1328 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v1_0_pause_dpg_mode()
1329 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v1_0_pause_dpg_mode()
1335 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v1_0_pause_dpg_mode()
1336 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v1_0_pause_dpg_mode()
1394 lower_32_bits(ring->gpu_addr)); in vcn_v1_0_pause_dpg_mode()
1396 upper_32_bits(ring->gpu_addr)); in vcn_v1_0_pause_dpg_mode()
1603 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vcn_v1_0_dec_ring_emit_ib()
1606 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vcn_v1_0_dec_ring_emit_ib()
1762 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vcn_v1_0_enc_ring_emit_ib()
1763 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vcn_v1_0_enc_ring_emit_ib()