Lines Matching refs:gpu_addr
409 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_mc_resume()
411 upper_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_mc_resume()
421 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v2_0_mc_resume()
423 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v2_0_mc_resume()
429 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_0_mc_resume()
431 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_0_mc_resume()
437 lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr)); in vcn_v2_0_mc_resume()
439 upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr)); in vcn_v2_0_mc_resume()
477 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
480 upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
498 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
501 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
518 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
521 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
530 lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
533 upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
974 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v2_0_start_dpg_mode()
978 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start_dpg_mode()
980 upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start_dpg_mode()
1145 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start()
1147 upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start()
1161 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_0_start()
1162 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start()
1170 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v2_0_start()
1171 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start()
1332 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_0_pause_dpg_mode()
1333 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v2_0_pause_dpg_mode()
1342 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v2_0_pause_dpg_mode()
1343 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v2_0_pause_dpg_mode()
1589 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vcn_v2_0_dec_ring_emit_ib()
1591 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vcn_v2_0_dec_ring_emit_ib()
1761 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vcn_v2_0_enc_ring_emit_ib()
1762 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vcn_v2_0_enc_ring_emit_ib()
1897 uint64_t addr = table->gpu_addr; in vcn_v2_0_start_mmsch()
2007 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_start_sriov()
2011 upper_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_start_sriov()
2025 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v2_0_start_sriov()
2029 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v2_0_start_sriov()
2040 lower_32_bits(adev->vcn.inst->gpu_addr + offset + in vcn_v2_0_start_sriov()
2045 upper_32_bits(adev->vcn.inst->gpu_addr + offset + in vcn_v2_0_start_sriov()
2059 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start_sriov()
2062 upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start_sriov()
2073 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start_sriov()
2077 upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start_sriov()