Lines Matching refs:internal
182 adev->vcn.inst[0].internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
183 adev->vcn.inst[0].internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
184 adev->vcn.inst[0].internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
185 adev->vcn.inst[0].internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
186 adev->vcn.inst[0].internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
187 adev->vcn.inst[0].internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
189 adev->vcn.inst[0].internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
191 adev->vcn.inst[0].internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
193 adev->vcn.inst[0].internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
195 adev->vcn.inst[0].internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
197 adev->vcn.inst[0].internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
1486 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0)); in vcn_v2_0_dec_ring_insert_start()
1488 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0)); in vcn_v2_0_dec_ring_insert_start()
1503 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[0].internal.cmd, 0)); in vcn_v2_0_dec_ring_insert_end()
1523 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.nop, 0)); in vcn_v2_0_dec_ring_insert_nop()
1544 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.context_id, 0)); in vcn_v2_0_dec_ring_emit_fence()
1547 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0)); in vcn_v2_0_dec_ring_emit_fence()
1550 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0)); in vcn_v2_0_dec_ring_emit_fence()
1553 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0)); in vcn_v2_0_dec_ring_emit_fence()
1556 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0)); in vcn_v2_0_dec_ring_emit_fence()
1559 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0)); in vcn_v2_0_dec_ring_emit_fence()
1562 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0)); in vcn_v2_0_dec_ring_emit_fence()
1585 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.ib_vmid, 0)); in vcn_v2_0_dec_ring_emit_ib()
1588 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.ib_bar_low, 0)); in vcn_v2_0_dec_ring_emit_ib()
1590 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.ib_bar_high, 0)); in vcn_v2_0_dec_ring_emit_ib()
1592 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.ib_size, 0)); in vcn_v2_0_dec_ring_emit_ib()
1601 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0)); in vcn_v2_0_dec_ring_emit_reg_wait()
1604 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0)); in vcn_v2_0_dec_ring_emit_reg_wait()
1607 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.gp_scratch8, 0)); in vcn_v2_0_dec_ring_emit_reg_wait()
1610 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0)); in vcn_v2_0_dec_ring_emit_reg_wait()
1635 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0)); in vcn_v2_0_dec_ring_emit_wreg()
1638 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0)); in vcn_v2_0_dec_ring_emit_wreg()
1641 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0)); in vcn_v2_0_dec_ring_emit_wreg()
1842 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0)); in vcn_v2_0_dec_ring_test_ring()
1844 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.scratch9, 0)); in vcn_v2_0_dec_ring_test_ring()