Lines Matching refs:gpu_addr
641 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v2_5_mc_resume()
643 upper_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v2_5_mc_resume()
652 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)); in vcn_v2_5_mc_resume()
654 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset)); in vcn_v2_5_mc_resume()
660 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_5_mc_resume()
662 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_5_mc_resume()
668 lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); in vcn_v2_5_mc_resume()
670 upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); in vcn_v2_5_mc_resume()
707 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
710 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
728 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
731 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
748 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
751 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
760 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
763 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
1152 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v2_5_start_dpg_mode()
1156 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_start_dpg_mode()
1158 upper_32_bits(ring->gpu_addr)); in vcn_v2_5_start_dpg_mode()
1334 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_start()
1336 upper_32_bits(ring->gpu_addr)); in vcn_v2_5_start()
1350 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_5_start()
1351 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v2_5_start()
1359 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v2_5_start()
1360 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v2_5_start()
1376 uint64_t addr = table->gpu_addr; in vcn_v2_5_mmsch_start()
1476 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v2_5_sriov_start()
1480 upper_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v2_5_sriov_start()
1493 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)); in vcn_v2_5_sriov_start()
1497 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset)); in vcn_v2_5_sriov_start()
1507 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + in vcn_v2_5_sriov_start()
1512 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + in vcn_v2_5_sriov_start()
1526 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_sriov_start()
1529 upper_32_bits(ring->gpu_addr)); in vcn_v2_5_sriov_start()
1539 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_sriov_start()
1543 upper_32_bits(ring->gpu_addr)); in vcn_v2_5_sriov_start()
1718 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_5_pause_dpg_mode()
1719 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v2_5_pause_dpg_mode()
1728 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v2_5_pause_dpg_mode()
1729 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v2_5_pause_dpg_mode()